Selective Underfill Assembly for Optical IC Restricted Zones
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Solution Overview
Problem
Existing underfill processes for optical packaging are unable to selectively control the location of underfill material, leading to leakage into restricted areas such as laser and V-groove zones, which compromises the performance and reliability of optical components.
Innovation Solution
A selective underfill process using pre-applied thermoset adhesive, strategically dispensed on a chip or substrate, which expands or spreads only into intended areas during thermocompression bonding, keeping restricted areas free of underfill material.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional underfill processes are used, then underfill material can be applied to the chip area, but underfill material leaks into restricted areas such as laser and V-groove zones
Solution Approach 1:
The patent applies underfill material to the chip area before bonding the chip to the substrate. This preliminary application allows the underfill to be strategically positioned in areas that will later be covered by the chip, preventing leakage into restricted zones while eliminating the need for post-bonding underfill application
Solution Approach 2:
The patent implements selective underfilling by applying underfill material only to specific regions of the chip area that are not restricted zones. This local quality approach ensures that underfill is present where needed for mechanical support and stress relief while absent from areas where it would interfere with optical components such as laser beams and V-grooves
2Manufacturing precision
If chemical barriers are used to prevent underfill leakage, then underfill can be contained, but the process becomes more complex and requires additional steps
Solution Approach 1:
The patent eliminates chemical barriers by applying underfill material before bonding, when the chip geometry itself serves as the containment structure. This preliminary timing approach removes the need for additional barrier materials and simplifies the overall process while maintaining effective underfill containment
Solution Approach 2:
The patent removes chemical barriers from the process entirely by changing the timing of underfill application. By applying underfill before bonding, the process extracts the barrier function from a separate material layer and replaces it with the structural geometry of the chip-substrate assembly
3Reliability
If separate curing steps are used for underfill, then underfill can be properly cured, but the manufacturing process becomes slower and more expensive
Solution Approach 1:
The patent merges the underfill curing step with the chip bonding process by applying underfill before bonding. This allows both the bonding adhesive and underfill material to be cured simultaneously in a single thermal processing step, eliminating separate curing operations and reducing overall manufacturing cycle time
Solution Approach 2:
The patent applies underfill material in advance before bonding, positioning it to be cured together with the bonding adhesive. This preliminary application timing enables the underfill to benefit from the bonding process thermal cycle, eliminating the need for separate post-bonding curing steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This process ensures reliable underfilling of intended areas while maintaining the performance and reliability of optical components by preventing underfill material from entering restricted zones, eliminating the need for chemical barriers and separate curing steps, thus being faster, easier, and cheaper than traditional methods.
Implementation Method 1
dispensing a thermoset adhesive on the first semiconductor device in one or more patterns on a surface of the first semiconductor device
Implementation Method 2
attaching a second semiconductor device to the surface of the first semiconductor device
Data Source
AI summary
Integrated circuit (IC) packages with pre-applied underfill in select areas, and methods of forming the same, are disclosed herein. In one example, an IC package includes a package substrate, a first IC die electrically coupled to the package substrate, a second IC die electrically coupled to the first IC die, and a thermoset adhesive that partially fills an area between the first IC die and the second IC die.