Area-Selective Via Deposition for Zero-Enclosure Metal Routing
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Solution Overview
Problem
As semiconductor technology advances towards smaller nodes, the challenges of reduced critical dimensions in multilevel interconnects (MLI) features lead to increased interconnect resistance, electromigration risk, and shorts between conductive elements, making it difficult to maintain electrical isolation and alignment in integrated circuit (IC) devices during back-end-of-line (BEOL) processing.
Innovation Solution
The implementation of area-selective deposition (ASD) operations, which selectively deposit conductive or insulating materials on exposed surfaces while avoiding deposition on dielectric surfaces, reducing the need for photolithography and etching processes, and allowing for zero-offset via positioning and increased via/metal density, thereby improving alignment and reducing manufacturing errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional photolithography and etching processes are used for patterning multilevel interconnects, then alignment and electrical isolation can be achieved, but manufacturing complexity increases and defect rates rise at smaller nodes
Solution Approach 1:
The patent extracts and eliminates the photolithography and etching steps from the traditional patterning process. Instead of using photoresist coating, exposure, and etching operations, the invention directly deposits conductive material through area-selective atomic layer deposition (ALD) only on desired interconnect regions, thereby removing the complex photolithography workflow while maintaining precise alignment and patterning capability at nanometer nodes
Solution Approach 2:
The area-selective ALD process is self-aligning by nature, as the deposited material automatically conforms to the underlying topography and selectively forms patterns based on surface energy differences. This self-service mechanism eliminates the need for separate alignment and patterning steps, reducing process complexity while achieving the required manufacturing precision for multilevel interconnects
2Productivity
If feature sizes are reduced to increase device density, then more interconnects can be packed, but interconnect resistance and electromigration risk increase
Solution Approach 1:
The patent changes the material deposition parameters by using area-selective atomic layer deposition with controlled cycle numbers and deposition rates. This allows precise control over metal film thickness and composition, enabling optimization of electrical properties such as conductivity and resistance. The selective deposition process also enables better material utilization and reduced void formation, improving interconnect reliability at reduced feature sizes
Solution Approach 2:
The invention employs composite material structures through area-selective deposition of multiple metal layers and dielectric materials. By selectively depositing different materials on different surfaces (e.g., metal on exposed interconnect regions, dielectric on protected regions), the process creates optimized composite structures that simultaneously achieve low resistance and high reliability in scaled interconnects
3Area of stationary object
If area-selective deposition is used to increase via and metal pattern density, then chip area decreases, but process control complexity increases
Solution Approach 1:
The area-selective ALD process inherently provides self-alignment and self-patterning capabilities through surface energy differences between exposed and protected regions. This self-service mechanism automatically ensures precise pattern formation and alignment without requiring complex external control systems, thereby reducing process control complexity while achieving high via and metal pattern density for reduced chip area
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
ASD operations enhance via and metal pattern densities, decrease chip area, improve IC device performance, and increase manufacturing yield by eliminating defects associated with traditional patterning and etching processes, resulting in a 4% area gain and reduced manufacturing time and costs.
Implementation Method 1
The implementation of area-selective deposition (ASD) operations, which selectively deposit conductive or insulating materials on exposed surfaces while avoiding deposition on dielectric surfaces
Data Source
AI summary
Provided is a method for manufacturing integrated circuit (IC) devices including the operations of forming a first metal pattern (Mx) on a semiconductor substrate, forming a first via pattern (Vx) on the first metal pattern using an area selective deposition (ASD) that includes first and second vias formed adjacent opposed edges or terminal portions of the first metal pattern, and forming a second metal pattern (Mx+1) on the first via pattern with substantially no pattern overlap to form a zero enclosure and wherein a pair of adjacent vias are separated by a distance corresponding to the smallest end-to-end metal pattern spacing permitted under a set of design rules applied during the design of the IC devices.