Selective Via Fill With Conformal Liner for Lower Via Resistance
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Solution Overview
Problem
In semiconductor device fabrication, particularly in copper interconnects, the thickness of barrier metal and liner layers in vias with small dimensions leads to high via resistance due to limited volume for copper filling, making it challenging to scale these layers while maintaining continuity, adhesion, and filling efficiency.
Innovation Solution
A method involving selective deposition of conductive materials and simultaneous liner formation on inner sidewalls of vias and trenches, allowing for partial or full filling of vias with conductive materials while forming a conformal liner, reducing via resistance and aspect ratio, using techniques like atomic layer deposition and chemical vapor deposition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If barrier metal and liner layers are made thicker to prevent diffusion and maintain continuity, then reliability of the interconnect structure is improved, but via resistance increases due to reduced copper filling volume
Solution Approach 1:
The patent applies different material properties to different locations: a first conductive material (e.g., ruthenium, cobalt, tungsten) is deposited selectively on the via bottom to provide local electrical connectivity and reduce resistance, while a second conductive material (e.g., copper) fills the via body. This local differentiation allows the via bottom to have high conductivity without requiring thick barrier/liner layers throughout the entire via, thus resolving the contradiction between reliability and via resistance.
2Object-affected harmful factors
If barrier metal and liner layers are scaled down to reduce via resistance, then via resistance decreases with more copper filling volume, but manufacturing precision becomes challenging to maintain layer continuity and adhesion
Solution Approach 1:
The patent changes the material parameter (type of conductive material) rather than simply reducing the thickness of barrier/liner layers. By using a first conductive material with appropriate deposition characteristics (e.g., atomic layer deposition for conformal coverage) on the via bottom, the system achieves reliable thin-film deposition without the adhesion and continuity problems associated with scaling down traditional barrier/liner stacks. This parameter change enables manufacturing precision to be maintained while achieving lower via resistance.
3Productivity
If via aspect ratio is reduced to improve copper filling efficiency, then productivity increases, but the via dimensions must be changed which may affect device design flexibility
Solution Approach 1:
The patent segments the via filling process into distinct stages: first depositing a conductive material on the via bottom, then filling the remaining via body with copper. This segmentation allows the via structure to maintain its original high aspect ratio design for device compatibility, while the segmented filling approach improves copper deposition efficiency by providing a nucleation layer that facilitates subsequent copper growth. Thus, productivity increases without compromising design flexibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces overall via resistance and simplifies the copper filling process by selectively depositing conductive materials at varying rates, ensuring effective liner formation and efficient interconnect formation in dual damascene processes.
Implementation Method 1
forming a passivation layer selectively on an exposed surface of a conductive layer
Implementation Method 2
forming a barrier layer selectively on inner sidewalls of the via and a trench formed in the dielectric layer
Implementation Method 3
selectively filling the via with a first conductive material at least partially and simultaneously depositing the first conductive material on the barrier layer on the inner sidewalls of the via and the trench, to form a liner on the inner sidewalls of the via and the trench
Implementation Method 4
using techniques like atomic layer deposition and chemical vapor deposition
Implementation Method 5
filling the remaining of the via and the trench with a second conductive material
Data Source
AI summary
A method of selectively filling a via with a simultaneous liner deposition in a semiconductor structure includes forming a passivation layer selectively on an exposed surface of a conductive layer within a via formed in a dielectric layer formed over the conductive layer, forming a barrier layer selectively on inner sidewalls of the via and a trench formed in the dielectric layer, selectively filling the via with a first conductive material at least partially and simultaneously depositing the first conductive material on the barrier layer on the inner sidewalls of the via and the trench, to form a liner on the inner sidewalls of the via and the trench, and filling the remaining of the via and the trench with a second conductive material.