Selective Via Liner Deposition for Lower Resistance Interconnects
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Solution Overview
Problem
As transistors and interconnects scale to the 3 nm node and beyond, increasing resistance in interconnect vias leads to performance degradation and power consumption issues, with conventional copper interconnect structures facing challenges in reducing via resistance and preventing copper diffusion.
Innovation Solution
A method involving the selective deposition of a metal liner on the barrier layer within microelectronic devices, where a self-assembled monolayer is used to prevent barrier layer growth on the via bottom, allowing selective growth on the sidewalls, and a passivation layer is formed to control metal liner deposition, reducing via resistance and copper corrosion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a barrier layer is deposited on the via bottom to prevent copper diffusion, then copper diffusion prevention is improved, but via resistance increases due to the high resistivity of the barrier layer
Solution Approach 1:
The patent applies different treatments to different locations: the via sidewalls receive a barrier layer for copper diffusion prevention, while the via bottom is passivated with a self-assembled monolayer to prevent barrier layer deposition. This local differentiation allows the barrier layer to protect against copper diffusion on sidewalls while eliminating its harmful resistive effect on the via bottom, where it is not needed for diffusion prevention.
2Object-affected harmful factors
If a metal liner is deposited on the barrier layer to reduce via resistance, then via resistance decreases, but deposition selectivity becomes difficult to achieve
Solution Approach 1:
The patent performs preliminary passivation of the via bottom with a self-assembled monolayer before barrier layer deposition. This preliminary action modifies the surface chemistry of the via bottom to be non-reactive toward the barrier layer precursor, ensuring that subsequent barrier layer and metal liner deposition occurs only on desired surfaces (sidewalls), achieving the required deposition selectivity without complex process control.
3Object-affected harmful factors
If the thickness of barrier layers is reduced to decrease via resistance, then via resistance decreases, but copper diffusion prevention capability is compromised
Solution Approach 1:
The patent extracts the barrier layer function from the via bottom location, where it is not needed for copper diffusion prevention. By removing the barrier layer from the via bottom through passivation, the design eliminates the trade-off between barrier thickness and via resistance, allowing the barrier layer to be optimized for sidewall protection while the via bottom maintains low resistance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces via resistance by at least 20% and improves deposition selectivity, maintaining performance and reducing power consumption in microelectronic devices.
Implementation Method 1
selectively depositing a self-assembled monolayer (SAM) on the metal material
Implementation Method 2
a self-assembled monolayer is used to prevent barrier layer growth on the via bottom
Implementation Method 3
passivating the metal material with an alkyl reactant to form a passivation layer on the metal material
Data Source
AI summary
Methods of forming devices comprise forming a dielectric material on a substrate, the dielectric layer comprising at least one feature defining a gap including sidewalls and a bottom. The methods include passivating a metal material at a bottom of the gap with an alkyl reactant to form a passivation layer on the metal material, the gap defined by the bottom and sidewalls comprising the dielectric material with having a barrier layer thereon. A metal liner is selectively deposited on the barrier layer on the sidewall over the passivation layer on the bottom.