Selective Via Post Interconnects for Registration-Tolerant Scaling
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Solution Overview
Problem
As integrated circuit (IC) dimensions scale down, the minimum distance between interconnect lines decreases rapidly due to registration errors, leading to increased susceptibility to shorts and time-dependent dielectric breakdown, which negatively impacts IC yield and reliability.
Innovation Solution
The implementation of selective via posts with a bottom lateral dimension smaller than the via opening, allowing for precise electrical connection between upper and lower level interconnect features while maintaining a minimum interconnect line spacing, independent of registration errors, through selective deposition techniques and dielectric backfilling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If interconnect dimensions are scaled down to increase integration density, then device capacity is improved, but the minimum distance between interconnect lines decreases rapidly due to registration errors, leading to increased susceptibility to shorts and dielectric breakdown
Solution Approach 1:
The interconnect structure is segmented into distinct functional regions: a via opening region for electrical connection and a spacing region for isolation. The via post is selectively formed only in the via opening region, while the spacing region maintains a larger distance between adjacent interconnect lines. This segmentation allows the minimum line spacing to be determined by the via post lateral dimension rather than registration errors, resolving the contradiction between scaling down for higher density and maintaining reliability.
Solution Approach 2:
The invention transitions from a two-dimensional planar spacing determination to a three-dimensional structure where the via post's lateral dimension (height in the vertical dimension) determines the minimum line spacing. By using the via post's vertical extent as the spacing determinant rather than relying on lateral registration accuracy, the design achieves better scalability and reduced susceptibility to shorts and dielectric breakdown.
2Productivity
If the minimum distance between interconnect lines is reduced to increase scaling, then interconnect density is improved, but registration errors uncontrollably reduce the minimum design spacing, impacting yield and reliability
Solution Approach 1:
The via post structure serves itself to define the minimum spacing requirement. The via post is formed to extend vertically from the first dielectric layer to the second dielectric layer, and its lateral dimension at any level automatically establishes the spacing boundary. This self-defining characteristic eliminates the need for precise lateral registration between layers, as the via post's own geometry determines the spacing, thereby improving manufacturing precision control.
Solution Approach 2:
The via post is formed in advance before final interconnect line placement, establishing a predetermined spacing boundary. The via post's lateral dimension is controlled during formation to ensure adequate spacing, and subsequent interconnect lines are positioned relative to this pre-established boundary. This preliminary action ensures that minimum design spacing is maintained independent of later registration errors.
3Productivity
If line spacing is decreased to improve scaling, then interconnect capacity is improved, but line edge roughness becomes a more significant fraction of CDs, increasing susceptibility to shorts and TDDB fails
Solution Approach 1:
The interconnect structure is divided into a via post region with controlled lateral dimensions and spacing regions with larger clearances. By segmenting the structure, the via post's lateral dimension becomes the controlling factor for minimum spacing rather than line edge roughness. This segmentation allows tighter spacing without proportionally increasing the impact of line edge roughness, as the via post provides a well-defined geometric boundary.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances scalability and reliability of IC interconnects by reducing the risk of shorts and dielectric breakdown, thereby improving IC yield and device performance.
Implementation Method 1
selective deposition techniques and dielectric backfilling
Data Source
Figure 1
Figure 2A~2B
Figure 3A
AI summary
Interconnect structures including a selective via post disposed on a top surface of a lower level interconnect feature, and fabrication techniques to selectively form such a post. Following embodiments herein, a minimum interconnect line spacing may be maintained independent of registration error in a via opening. In embodiments, a selective via post has a bottom lateral dimension smaller than that of a via opening within which the post is disposed. Formation of a conductive via post may be preferential to a top surface of the lower interconnect feature exposed by the via opening. A subsequently deposited dielectric material backfills portions of a via opening extending beyond the interconnect feature where no conductive via post was formed. An upper level interconnect feature is landed on the selective via post to electrically interconnect with the lower level feature.