Semiconductor Timing Circuits: Selective Wire Widths Against Opens
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Solution Overview
Problem
Integrated circuits are susceptible to manufacturing defects, particularly wire opens, as wire sizes decrease and spacing between adjacent wires decreases, leading to performance issues and increased power consumption.
Innovation Solution
Implement wire width adjustment by widening selected wires adjacent to open spaces, and use electrical performance modeling to optimize wire widths and positions, reducing the likelihood of defects while maintaining performance specifications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If wire spacing is decreased to increase circuit density, then productivity is improved, but manufacturing precision deteriorates due to increased susceptibility to wire opens
Solution Approach 1:
The patent applies preliminary action by inserting redundant wires into the circuit design before manufacturing. These backup wires are pre-positioned adjacent to primary wires and connected to the same logic elements, so that if a wire open defect occurs during manufacturing, the redundant wire can immediately compensate without requiring post-manufacturing intervention.
Solution Approach 2:
The patent changes the structural parameter of the wire network by adding redundant parallel wire paths. This parameter change increases the overall wire capacity and provides alternative current paths, thereby maintaining manufacturing precision (wire integrity) even when spacing is decreased to improve circuit density.
2Reliability
If redundant wire features are added to protect against manufacturing defects, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent applies local quality by selectively placing redundant wires only in specific locations where they are most needed—adjacent to primary wires that connect to critical logic elements. This localized approach provides defect protection (improving reliability) without unnecessarily increasing device complexity across the entire circuit, as redundant wiring is added only where it provides maximum benefit.
3Manufacturing precision
If wire width is increased to reduce manufacturing defects, then manufacturing precision is improved, but power consumption increases due to increased capacitive coupling
Solution Approach 1:
The patent applies partial action by adding only the necessary minimum redundancy to achieve defect protection, rather than uniformly increasing wire width across all circuits. The redundant wires provide sufficient backup capacity to handle wire opens without the excessive capacitive coupling that would result from significantly widening all wires, thereby maintaining acceptable power consumption levels while improving manufacturing precision.
Data Source
AI summary
A semiconductor device includes a first circuit element, a layer of dielectric material, a first wire and a second wire in the layer of dielectric material, and an array of wires in the layer of dielectric material, wherein a first wire at a first track in the array of wires is electrically connected to the first circuit element, the first wire having a first width, a second wire at a second track in the array of wires has a second width different from the first width, and a third track in the array of wires between the first track and the second track is an empty track, and wherein the first wire is asymmetric with respect to the first track in the array of wires.