Selective Write Assist Control for Low Power Memory
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Solution Overview
Problem
In low power memory circuits, the generation of negative voltages for write assist operations leads to unnecessary power consumption due to the initiation of write assist circuits for all subarrays, even when they are not the target of a write operation, resulting in inefficient power usage.
Innovation Solution
Implementing separate write assist circuits for each subarray and using distinct write boost signals or masking mechanisms to selectively apply the write boost signal only to the subarrays that are the target of a writing operation, thereby preventing unnecessary charging of boost capacitors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a common write boost signal is used to drive all write assist circuits, then the control structure is simple, but unnecessary power consumption occurs in subarrays that are not the target of write operations
Solution Approach 1:
The patent divides the memory array into multiple independently controllable subarrays (first subarray, second subarray, etc.), each with its own write assist circuit and selective control. This segmentation allows the write boost signal to be applied only to specific subarrays that are targets of write operations, rather than all subarrays simultaneously, thereby reducing unnecessary power consumption while maintaining operational effectiveness.
2Reliability
If write assist circuits are initiated for all subarrays using a common write boost signal, then the write operation coverage is comprehensive, but power consumption increases due to unnecessary negative voltage generation in non-target subarrays
Solution Approach 1:
The patent applies different control conditions to different subarrays based on their specific operational needs. Each subarray receives the write boost signal only when it is the target of a write operation, as determined by local control logic. This local quality approach ensures that write assist circuits are activated only where necessary, maintaining comprehensive write operation coverage while avoiding unnecessary power consumption in non-target subarrays.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power consumption by avoiding unnecessary charging of boost capacitors in non-target subarrays and ensures precise timing for write operations, preventing timing violations and improving the efficiency of memory circuit operations.
Implementation Method 1
The negative voltage is typically formed by grounding a first terminal of a boost capacitor and applying a positive voltage to a second terminal of the boost capacitor. This causes the boost capacitor to charge to produce a negative voltage between the first and second terminals.
Data Source
AI summary
A memory circuit includes a set of subarrays of memory cells and a set of write assist circuits for generating negative voltages on bitlines pertaining to the set of subarrays, respectively. A set of distinct signals initiate the write assist circuits in generating the negative voltages for subarrays, respectively. The distinct signals may have particular state to cause a subset of the write assist circuits to generate the negative voltages if the corresponding subarrays are target of a writing operation, and another state to cause another subset of the write assist circuits to not generate the negative voltages if the corresponding subarrays are not target of the writing operation. This avoids the unnecessary generation of negative voltages for subarrays that are not the target of a writing operation so as to reduce power consumption. The generation of the distinct signals may be based on a set of write mask signals.