Selective Write-Back Error Scrubbing in Semiconductor Memory
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Solution Overview
Problem
Semiconductor memory devices, particularly DRAMs, face increased errors due to reduced fabrication design rules, necessitating effective error correction methods to maintain data integrity and efficiency.
Innovation Solution
A method involving a semiconductor memory device with a memory cell array and an error correction circuit that selectively corrects errors by accessing pages, reading data units with parity data, and writing back corrected data, thereby reducing power consumption and improving data integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction is performed on all data units, then data integrity is improved, but power consumption increases
Solution Approach 1:
The patent applies local quality by performing error correction selectively on specific data units (sub-pages) rather than uniformly across all data. The error correction circuit identifies and corrects errors only in sub-pages where errors are detected, while leaving error-free sub-pages uncorrected, thereby reducing unnecessary power consumption while maintaining data integrity where needed.
Solution Approach 2:
The patent implements partial action by performing error correction on only a portion of the data units (those containing errors) rather than all data units. The error correction circuit processes sub-pages selectively based on error detection results, applying correction only where necessary to achieve the desired data integrity with reduced power consumption.
2Quantity of substance
If fabrication design rules are reduced to increase memory density, then storage capacity is improved, but error rate increases
Solution Approach 1:
The patent addresses the increased error rate from reduced fabrication design rules by implementing dynamic error correction parameters. The system adjusts error correction operations based on detected error conditions, applying correction strength and frequency adapted to the actual error rate observed in the high-density memory, thereby maintaining reliability despite smaller feature sizes.
Solution Approach 2:
The patent uses parity data as a copy or replica of the original data for error detection and correction purposes. By maintaining and comparing against this parity copy, the system can identify and correct errors in the high-density memory without requiring physical redundancy of the entire data set, thus preserving memory density while improving reliability.
3Use of energy by moving object
If selective write-back of corrected data is implemented, then power consumption is reduced, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the data into sub-pages and processing them independently through the error correction pipeline. This segmentation allows the control logic to manage selective write-back operations on a per-sub-page basis, reducing the complexity of coordinating large-scale selective operations while enabling fine-grained power optimization through targeted corrections.
Data Source
AI summary
A method of scrubbing errors from a semiconductor memory device including a memory cell array and an error correction circuit, can be provided by accessing a page of the memory cell array to provide a data that includes sub units that are separately writable to the page of memory and to provide parity data configured to detect and correct a bit error in the data and selectively enabling write-back of a selected sub unit of the data responsive to determining that the selected sub unit of data includes a correctable error upon access as part of an error scrubbing operation.