Programmable Selector Circuit for Flexible PLD Resource Mapping
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Solution Overview
Problem
Programmable logic devices (PLDs) face challenges in efficiently implementing user functions due to limited resource availability, requiring burdensome design modifications or more expensive devices with additional resources.
Innovation Solution
The implementation of a PLD architecture that includes programmable interconnect circuits, logic circuits, one-bit registers, and selector circuits, allowing for flexible configuration and mapping of next-state and output functions to optimize resource utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional PLD architectures with fixed configurable resources are used, then device structure is simple, but resource utilization is inefficient and design flexibility is limited
Solution Approach 1:
The patent implements dynamic resource allocation by making the interconnect structure reconfigurable. The interconnect includes selectable connections that can be programmed to establish different routing paths between logic resources, allowing the device topology to adapt dynamically to different design requirements rather than being fixed statically.
Solution Approach 2:
The patent creates universal logic resources that can perform multiple functions. The configurable logic elements and interconnect structure are designed to accommodate various logic functions and routing patterns, allowing the same hardware resources to serve different purposes based on programming configuration rather than being dedicated to single functions.
2Adaptability or versatility
If PLD has limited configurable resources, then device cost is reduced, but capability to implement complex user functions is insufficient
Solution Approach 1:
The patent enables continuous utilization of configurable resources through efficient resource sharing and reuse mechanisms. The reconfigurable interconnect allows logic resources to be dynamically allocated and reused across different functions and time periods, ensuring that resources remain continuously productive rather than idle, thereby maximizing the effective capability of limited hardware resources.
3Productivity
If more configurable resources are added to PLD, then resource utilization improves, but device cost and complexity increase
Solution Approach 1:
The patent merges multiple interconnect structures into a unified reconfigurable interconnect fabric. Instead of providing separate dedicated interconnects for different logic resources, the patent combines them into a shared structure with selectable connections that can dynamically route signals between any logic resources, reducing overall interconnect complexity while improving resource utilization efficiency.
Data Source
AI summary
A PLD is configurable to efficiently implement a wide variety of user functions. The PLD includes a programmable interconnect circuit, programmable logic circuits, one-bit registers, selector circuits, and input/output blocks. The programmable interconnect circuit is configurable to connect the signal lines of its output ports to the signal lines of its input ports. The programmable logic circuits are configurable to implement a programmable function generating one-bit signal values from a respective output port of the programmable interconnect circuit. The one-bit registers store a respective one of these one-bit signal values. The programmable selector circuits are each coupled to output ports of a plurality of the one-bit registers, with each of these one-bit registers coupled to a respective one of the programmable logic circuits. The programmable input/output blocks are each coupled to an output port of a respective programmable selector circuit and to a respective input port of the programmable interconnect circuit.