Upper and Lower Selector Layout for Dense Memory Interconnects

The semiconductor device is divided into multiple banks, each with its own independent selector and interconnection. This segmentation allows only the necessary banks to be activated for each operation, reducing the number of simultaneously active interconnections and thus lowering power consumption while maintaining high integration density across the entire device.

The patent transitions from a planar interconnection architecture to a three-dimensional stacked architecture with multiple layers of word lines and channel structures. This vertical stacking enables higher integration density without proportionally increasing the number of long-haul signal interconnections, as memory cells are accessed through vertical channels rather than requiring extensive lateral routing.

The interconnection network is segmented into multiple independent bank-level interconnections rather than a single large-scale interconnection network. Each bank has its own selector and word line interconnections, which simplifies the control logic and reduces the overall complexity by breaking down the large interconnection problem into smaller, manageable units.

The selector structures serve multiple functions: they act as row decoders for word line selection, column selectors for bit line selection, and bank-level multiplexers for interconnection management. This multi-functionality reduces the need for separate dedicated structures for each function, thereby reducing overall interconnection complexity.