Selector Transistor Driving Ability Control in Non-Volatile Memory
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Solution Overview
Problem
In non-volatile memory devices, the varying load capacity during sequential and non-sequential access operations leads to increased consumption current and access time due to redundant driving ability and excessive voltage boosting.
Innovation Solution
A non-volatile memory device with a control circuit that adjusts the driving ability of selector transistors based on the transition of memory cells within a block, using a multi-column selection access method to reduce consumption current and shorten access time by varying the number of selector transistors operated during sequential and non-sequential access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If circuits are operated based on load capacity required during non-sequential access operation, then driving ability during non-sequential access is sufficient, but consumption current increases and access time increases due to redundant driving ability during sequential access operation
Solution Approach 1:
The patent applies dynamics by making the driving ability of selector transistors adjustable based on access operation type. The control circuit dynamically changes the number of selector transistors operated - using fewer transistors during sequential access and more transistors during non-sequential access, thereby adapting the system's driving capability to actual load requirements and reducing redundant power consumption
Solution Approach 2:
The patent changes the parameter of transistor driving ability based on access mode. By detecting whether the access is sequential or non-sequential, the control circuit adjusts the driving ability parameter of selector transistors accordingly, optimizing the balance between reliable operation and power consumption for each access scenario
2Reliability
If circuits are operated based on load capacity required during non-sequential access operation, then driving ability during non-sequential access is sufficient, but access time increases due to excessive voltage boosting and regulating time
Solution Approach 1:
The system dynamically adjusts voltage boosting based on access type. During sequential access, the control circuit reduces or eliminates excessive voltage boosting since fewer transistors need to be operated, thereby reducing the regulating time and shortening access time. During non-sequential access, full voltage boosting is applied to ensure sufficient driving ability
Solution Approach 2:
The patent applies partial action by using only the necessary amount of voltage boosting and transistor operation for each access type. Instead of always applying full voltage boosting and operating all selector transistors, the system applies partial action during sequential access where fewer resources are needed, thereby reducing access time while maintaining sufficient driving ability
3Measurement precision
If four column lines are selected for reading out memory cell using MirrorBit architecture, then data reading accuracy is improved, but number of switching elements increases leading to increased load capacity variation
Solution Approach 1:
The patent makes the number of operated switching elements dynamic based on access type. During sequential access, the control circuit operates fewer selector transistors since the access pattern allows for optimized transistor usage. During non-sequential access, all necessary transistors are operated to ensure proper signal routing and data reading accuracy
Solution Approach 2:
The system changes the operational parameter of switching elements based on access mode. By detecting sequential versus non-sequential access, the control circuit adjusts which switching elements are activated and how many are operated, optimizing the balance between data reading accuracy and device complexity for each access scenario
Data Source
AI summary
The control method includes a step of varying driving ability of a selector transistor which selects a diffusion layer in a selected memory cell and a diffusion layer of at least one non-selected memory cell which adjoins to the selected memory cell when the selected memory cell makes transition from a memory cell at one end to a memory cell at other end within a memory block.