Selectorless 3D Memory Using Magnetic Junctions
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Solution Overview
Problem
Three-dimensional (3D) stackable memory arrays face high power requirements, limiting their integration into technologies like system-on-a-chip (SoC) devices, despite their potential for increased areal memory density.
Innovation Solution
The development of selectorless memory cells using magnetic junctions programmable via spin-orbit interaction torque and voltage-controlled magnetic anisotropy, which eliminate the need for selection devices, reducing area and voltage requirements and enabling 3D memory arrays with improved integration capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If 3D stackable memory arrays use traditional selection devices (transistors), then memory cell selectivity is improved, but power consumption increases and area requirements increase
Solution Approach 1:
The patent removes the transistor selection device from the memory cell structure, extracting the high-power component that was causing excessive power consumption. The selection function is replaced by a selectorless magnetic junction design that achieves cell selection through magnetic anisotropy control without requiring high-power transistor switching.
Solution Approach 2:
The patent replaces the mechanical/electronic transistor switching mechanism with a magnetic field-based selection mechanism. The magnetic junction uses voltage-controlled magnetic anisotropy to enable selective writing and reading operations without the need for transistor gate switching, substituting the high-power electronic control mechanism with a lower-power magnetic control mechanism.
2Reliability
If 3D stackable memory arrays use traditional selection devices (transistors), then memory cell selectivity is improved, but device area increases
Solution Approach 1:
The patent extracts and removes the transistor component from each memory cell, eliminating the need for gate electrodes, source/drain regions, and associated interconnect structures. This extraction of the selection device dramatically reduces the area occupied by each memory cell while maintaining selectivity through the magnetic junction's intrinsic properties.
Solution Approach 2:
The patent merges the selection function and storage function into a single magnetic junction structure. The magnetic junction simultaneously performs cell selection through its magnetic anisotropy characteristics and stores data through its magnetic state, eliminating the need for separate transistor and memory element components and reducing overall cell area.
3Reliability
If 3D stackable memory arrays use traditional selection devices, then memory access control is improved, but integration capability into SoC devices deteriorates
Solution Approach 1:
The patent adopts a simplified magnetic junction design that can be easily fabricated and integrated without requiring complex transistor structures. The selectorless design uses readily available magnetic materials and straightforward fabrication processes, making the memory array more adaptable for integration into system-on-chip devices where space and process compatibility are critical.
Solution Approach 2:
The patent changes the fundamental operating parameters of the memory cell from transistor-based voltage control to magnetic field control. This parameter change enables the memory to operate with lower voltage requirements and different timing characteristics that are more compatible with modern SoC integration requirements, improving adaptability while maintaining access control through magnetic anisotropy management.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces power consumption and enhances memory density, allowing 3D memory arrays to be integrated into additional technologies with modest voltage requirements and high noise margins, while maintaining scalability and stackability.
Implementation Method 1
The first and second magnetic junctions are each programmable using a spin-orbit interaction torque
Implementation Method 2
The selectorless memory cell includes first and second magnetic junctions. The first and second magnetic junctions are each programmable using a spin-orbit interaction torque
Data Source
AI summary
A memory device and method for providing the memory device are described. The memory device includes word lines, a first plurality of bit lines, a second plurality of bit lines and selectorless memory cells. Each selectorless memory cell is coupled with a word line, a first bit line of the first plurality of bit lines and a second bit line of the second plurality of bit lines. The selectorless memory cell includes first and second magnetic junctions. The first and second magnetic junctions are each programmable using a spin-orbit interaction torque. The word line is coupled between the first and second magnetic junctions. The first and second bit lines are coupled with the first and second magnetic junctions, respectively. The selectorless memory cell is selected for a write operation based on voltages in the word line, the first bit line and the second bit line.