Self-Adaptive Chip Architecture for Fast Dynamic Reconfiguration
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Solution Overview
Problem
Current ASIC and FPGA chips face limitations in dynamic reconfiguration and adaptability, with ASICs being inflexible and costly to update, and FPGAs having slow reconfiguration speeds due to large configuration data, making it difficult to achieve real-time dynamic reconstruction and multi-purpose functionality.
Innovation Solution
A self-adaptive chip with dynamically reconfigurable cells that can execute different functions and connect with neighboring cells for data exchange, allowing for fast reconfiguration and implementation of infinite circuit algorithms in a finite area, with the ability to adjust internal structure and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If ASIC is used for fixed-function integrated circuits, then manufacturing cost and power consumption are reduced, but adaptability and reconfiguration capability are lost
Solution Approach 1:
The chip is divided into multiple independently reconfigurable regions, each capable of being configured for different functions. This segmentation allows partial reconfiguration without affecting the entire chip, enabling adaptability while maintaining manufacturing efficiency through standardized region designs.
Solution Approach 2:
The patent implements dynamic reconfiguration capability where the chip structure can be modified during operation. Configuration data can be updated to change the functionality of reconfigurable regions, allowing the system to adapt to different computational requirements while maintaining a fixed physical structure that can be manufactured using standard ASIC processes.
2Adaptability or versatility
If FPGA is used for reconfigurable chips, then adaptability is improved, but reconfiguration time increases due to large configuration data
Solution Approach 1:
The patent extracts only the essential configuration parameters needed for reconfiguration, rather than storing complete circuit descriptions. By identifying and retaining only the critical configuration data required to redefine logic cell connections and functions, the reconfiguration time is significantly reduced while maintaining full adaptability.
Solution Approach 2:
The patent changes the nature of configuration data from comprehensive circuit descriptions to compact parameter sets that define logic cell behavior and connections. This parameter-based configuration approach reduces the amount of data that needs to be loaded and processed during reconfiguration, enabling faster adaptation while preserving full functional flexibility.
3Adaptability or versatility
If complete reconfiguration is performed, then functional adaptability is achieved, but processing continuity is interrupted
Solution Approach 1:
The chip is divided into multiple independently reconfigurable regions that can be configured separately. This allows one region to be reconfigured while other regions continue to process data, maintaining overall system operation and processing continuity during adaptation.
Solution Approach 2:
The patent enables periodic or scheduled reconfiguration of different chip regions, allowing the system to alternate between processing and reconfiguration phases for different segments. This periodic approach ensures that reconfiguration occurs without completely interrupting system functionality, as other regions continue to operate.
4Adaptability or versatility
If chip scale increases to provide more functions, then functionality is improved, but reconfiguration time increases
Solution Approach 1:
Large-scale chips are divided into multiple smaller reconfigurable regions, each with its own configuration parameters. This segmentation allows independent configuration of each region, reducing the total reconfiguration time compared to configuring the entire large chip at once, while still providing extensive overall functionality through the combination of multiple regions.
Solution Approach 2:
For large-scale chips, the patent extracts and prioritizes the most critical configuration parameters for each region, enabling selective reconfiguration of only the necessary parts of the chip. This approach reduces reconfiguration time by focusing on essential parameter updates rather than complete system reconfiguration.
Data Source
AI summary
Disclosed are a self-adaptive chip (100) and configuration method. The self-adaptive chip includes: a plurality of dynamically reconfigurable cells arranged in an array, each of the plurality of dynamically reconfigurable cells being capable of being dynamically reconfigured as needed to execute different operating functions and/or input-output control functions, wherein, each of the plurality of dynamically reconfigurable cells is connected to multiple neighboring dynamically reconfigurable cells, to acquire data from one or more of the multiple neighboring dynamically reconfigurable cells, and output an operation result based on the data to at least one neighboring dynamically reconfigurable cell.