Self-Adhesive Protective Layer for Flip-Chip Packaging

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Solution Overview

Problem

Conventional flip-chip packaging methods are complex and inefficient, leading to high processing costs due to the need for an underfill operation to couple chips and substrates.

Innovation Solution

A method using a chip with a self-adhesive protective layer and a substrate with exposed bonding fingers, where the chip is laminated onto the substrate via the protective layer, allowing electrical connection and optional adhesive dispensing to reinforce bonding, thereby simplifying the packaging process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional underfill operation is performed to couple chip and substrate, then bonding reliability is improved, but fabrication complexity increases and processing efficiency decreases

Engineering Contradiction:
Improvebonding reliabilityVSAvoidfabrication complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines the protective layer and adhesive layer into a single integrated structure. The protective layer on the chip is designed to serve dual functions: protecting the bumps and providing adhesive bonding capability to the substrate, thereby eliminating the need for separate underfill operation and reducing fabrication complexity while maintaining bonding reliability

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The protective layer is designed with multi-functionality, serving both as a protective barrier for the bumps and as an adhesive bonding agent. This universal layer performs multiple functions that were previously required separate components or operations, streamlining the fabrication process

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If conventional underfill operation is performed to couple chip and substrate, then bonding reliability is improved, but processing time and cost increase

Engineering Contradiction:
Improvebonding reliabilityVSAvoidprocessing efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

By merging the protective layer and adhesive function into one integrated layer, the patent eliminates the separate underfill dispensing and curing steps. This reduces processing time and improves productivity while the adhesive properties of the protective layer ensure bonding reliability is maintained

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The protective layer is pre-formed on the chip with adhesive properties before mounting. This preliminary preparation eliminates the need for subsequent underfill operation, streamlining the process and improving productivity while ensuring reliable bonding from the outset

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach streamlines the fabrication process, reduces costs, and enhances the efficiency of chip-substrate coupling, making it suitable for mass production by eliminating the need for extensive adhesive dispensing and underfill operations.

Implementation Method 1

a self-adhesive protective layer formed on the first surface and leaving the bumps exposed, the bumps protruding from the self-adhesive protective layer, wherein the self-adhesive protective layer is made of a photosensitive adhesive, a thermosetting adhesive, or an dielectric material

Methodology Applied
Scientific EffectAdhesive: Adhesive

Implementation Method 2

The chip and the substrate are laminated together by irradiation lamination, heat lamination, or thermal/sound wave lamination, to allow the chip to be coupled to the substrate via the self-adhesive protective layer

Methodology Applied
Scientific EffectPhotopolymerisation: Photopolymerisation

Implementation Method 3

The chip and the substrate are laminated together by irradiation lamination, heat lamination, or thermal/sound wave lamination

Methodology Applied
Scientific EffectHeating: Heating

Implementation Method 4

The chip and the substrate are laminated together by irradiation lamination, heat lamination, or thermal/sound wave lamination

Methodology Applied
Scientific EffectUltrasonic Vibration: Ultrasonic Vibration

Data Source

PatentUS7951644B2Semiconductor device and method for fabricating the same
Publication Date: 2011.05.31 UTAC HEADQUARTERS PTE LTD
  • US7951644B2 patent drawing
  • US7951644B2 patent drawing
  • US7951644B2 patent drawing

AI summary

A semiconductor device and a method for fabricating the same, including: a substrate having a mounting surface formed with a plurality of bonding fingers and covered with an insulating layer, the insulating layer having an opening formed therein for exposing the bonding fingers; and a chip coupled to the substrate and including a body, a self-adhesive protective layer, and a plurality of bumps protruding from the self-adhesive protective layer. The self-adhesive protective layer is formed on the chip but leaves the bumps exposed. The self-adhesive protective layer is made of a photosensitive adhesive, thermosetting adhesive, or dielectric material. The chip is coupled to the substrate via the self-adhesive protective layer, thus allowing the bumps to be electrically connected to the bonding fingers and at least an end of the opening to be exposed. The method enables a more streamlined manufacturing process and lower fabrication costs by dispensing with adhesive dispensing.