Self-Adjusting DLL Circuit for Accurate Clock Delay Matching
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Solution Overview
Problem
Conventional delay locked loop (DLL) circuits in semiconductor devices require extensive testing to adjust delay amounts, leading to increased production time due to differences in delay paths among devices, as the initial delay replica model is not accurately reflective of actual delays in internal circuits.
Innovation Solution
A self-adjusting DLL circuit with a delay replica modeling unit that compares phases between internal and feedback clocks, allowing for real-time adjustment of transfer delay amounts through a delay replica adjustment signal, enabling the circuit to synchronize clocks without external testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a conventional delay locked loop circuit uses a fixed delay replica model, then the circuit structure is simple, but the manufacturing precision of clock synchronization is poor due to delay path variations among devices
Solution Approach 1:
The delay replica model is transformed from a fixed structure to a dynamically adjustable one. The patent introduces a delay adjustment unit that can modify the delay amount of the delay replica model based on feedback from phase comparison, enabling the circuit to adapt to delay path variations among different devices and improve manufacturing precision.
Solution Approach 2:
A feedback mechanism is implemented where the phase comparison unit compares the phase of the internal clock with the feedback clock, and the delay adjustment unit adjusts the delay replica model based on this comparison result. This closed-loop feedback system enables automatic compensation for delay variations, improving clock synchronization precision without requiring complex external testing.
2Manufacturing precision
If extensive testing is performed to adjust delay amounts for each device, then manufacturing precision improves, but productivity decreases due to increased production time
Solution Approach 1:
The delay locked loop circuit is designed to automatically adjust its own delay replica model without external intervention. The circuit performs self-calibration by comparing phases and adjusting delay amounts autonomously, eliminating the need for extensive external testing for each device and thereby maintaining high productivity while achieving accurate delay matching.
Solution Approach 2:
The delay adjustment is performed automatically during the initial operation of the circuit rather than requiring separate testing steps. The self-adjusting mechanism enables the circuit to reach optimal synchronization state during normal operation, eliminating post-manufacturing testing and improving production efficiency.
3Measurement precision
If the delay replica model accurately reflects actual internal circuit delays, then clock synchronization precision improves, but the device complexity increases due to additional adjustment mechanisms
Solution Approach 1:
The delay adjustment unit is integrated within the existing delay locked loop circuit structure, merging the adjustment function with the delay replica model rather than adding completely separate external adjustment circuits. This integration achieves accurate delay matching while minimizing increases in overall device complexity.
Data Source
AI summary
A semiconductor device includes a delay locked loop unit configured to compare a phase of an internal clock with a phase of a feedback clock to delay the internal clock by a delay amount corresponding to a comparison result, and to output a delay locked clock, a delay replica modeling unit configured to output the feedback clock by reflecting a transfer delay amount of the internal clock used in an internal circuit into the delay locked clock, and to adjust the transfer delay amount in response to a delay replica adjustment signal, and a delay replica adjustment signal generation unit configured to compare the phase of the feedback clock with a phase of the delay locked clock, and to set a value of the delay replica adjustment signal in response to a comparison result.