Self-Align Mask Layer for NAND Flash Gate Fabrication
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Solution Overview
Problem
The existing NAND type flash memory fabrication process requires multiple lithographic etching steps, leading to increased costs, time consumption, and a high risk of short circuits due to micro-bridges formed between conductive layers, especially as line widths decrease.
Innovation Solution
A method is introduced that reduces the number of masks needed by using a self-align mask layer to define the pattern of the floating and control gates, eliminating the need for direct lithographic etching and thereby preventing short circuits, while also increasing integration and reducing manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple lithographic etching steps are used to form floating gate and control gate, then the gates can be defined with good precision, but the manufacturing cost increases and fabrication time is consumed
Solution Approach 1:
The patent applies preliminary action by pre-forming a self-align mask layer before forming the conductive layers. This mask layer is created in advance and automatically aligns with the isolation structures, eliminating the need for subsequent lithographic alignment steps. The self-align mask layer serves as a pre-prepared guide that defines the gate patterns without requiring additional complex lithography processes.
Solution Approach 2:
The self-align mask layer performs the dual function of both masking and alignment reference. It automatically defines the pattern boundaries for both the floating gate and control gate through its inherent alignment with the isolation structures, making the system self-sufficient in terms of pattern definition without external lithographic intervention.
2Ease of manufacture
If direct etching of conductive layer is used to form floating gate and control gate, then the fabrication process is simplified, but micro-bridges are likely formed between adjacent conductive layers causing short-circuit
Solution Approach 1:
The self-align mask layer acts as an intermediary element between the isolation structures and the conductive layers. It provides a physical barrier and alignment reference that prevents direct contact between adjacent conductive layers, thereby eliminating micro-bridge formation. The mask layer mediates the spatial relationship between conductive features, ensuring proper separation while maintaining fabrication simplicity.
3Manufacturing precision
If more masks are used in lithographic etching process, then the gate patterns can be defined more accurately, but the manufacturing cost increases
Solution Approach 1:
The self-align mask layer serves multiple functions simultaneously: it acts as an etch mask, an alignment reference, and a pattern definition template. This multi-functional element eliminates the need for separate alignment marks and multiple lithographic steps, achieving high pattern accuracy while reducing the overall number of manufacturing steps and associated costs.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces manufacturing costs, prevents short circuits, and enhances device integration by avoiding micro-bridges, allowing for the fabrication of NAND type flash memory with improved reliability and efficiency.
Implementation Method 1
a tunneling dielectric layer is formed on the substrate
Implementation Method 2
a plurality of doped regions is formed in the substrate on both sides of the second conductive layer
Data Source
AI summary
A method for fabricating a non-volatile memory is described. A substrate having isolation structures is provided. These isolation structures protrude from the substrate, and a first mask layer is formed on the substrate between the isolation structures. A second mask layer is formed on the substrate. The second and the first mask layers are patterned to form openings exposing part of the surface of the substrate and the isolation structures. A tunneling dielectric layer and a first conductive layer are formed on the substrate. The first conductive layer is filled in the opening, and is divided into blocks by the isolation structures, the second mask layer, and the first mask layer. An inter-gate dielectric layer is formed on the substrate. A second conductive layer is formed on the substrate to fill up the openings. Doped regions are formed in the substrate on both sides of the second conductive layer.