Self-Aligned 2D Transistor Channel for Low-Overlap Source/Drain
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Solution Overview
Problem
Managing short channel effects and achieving effective source drain doping in 2D transistors, such as 2D transition metal dichalcogenide (TMD) and carbon nanotube transistors, is challenging due to the limitations of traditional implantation and diffusion methods.
Innovation Solution
The development of a self-aligned process for forming integrated circuits with 2D transistors, where the channel region is aligned with the gate electrode, resulting in minimal overlap and controlled overlap regions with the source/drain regions, using materials like titanium nitride and high-K dielectric materials to enhance electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional implantation and diffusion methods are used for source drain doping in 2D transistors, then doping can be achieved, but the process is difficult to implement and may not be available for 2D-TMD and CNT transistors
Solution Approach 1:
The patent extracts the doping function from traditional implantation/diffusion methods and implements it through in-situ material deposition. The source and drain regions are formed by depositing conductive materials (such as titanium nitride) directly onto the channel region, eliminating the need for complex implantation and diffusion processes that are difficult to apply to 2D-TMD and CNT transistors.
Solution Approach 2:
The patent replaces the mechanical/physical processes of ion implantation and thermal diffusion with a deposition-based approach. Conductive materials are deposited using physical vapor deposition (PVD) or chemical vapor deposition (CVD) techniques, substituting the mechanical impact and thermal diffusion mechanisms with controlled material deposition that is more compatible with 2D transistor fabrication.
2Reliability
If the channel region overlaps with source/drain regions, then electrical connection is improved, but induced charges and parasitic capacitance increase
Solution Approach 1:
The patent applies local quality by creating a non-uniform overlap configuration. The channel region has minimal overlap with the source region but controlled overlap with the drain region. This asymmetric design optimizes electrical connection where needed while minimizing parasitic capacitance in critical areas, allowing different portions of the device to have different overlap characteristics suited to their functional requirements.
Solution Approach 2:
The patent implements partial overlap rather than complete or excessive overlap between the channel and source/drain regions. By providing just enough overlap to ensure adequate electrical connection while avoiding excessive overlap, the design achieves the minimum necessary action to maintain reliability without generating unnecessary parasitic capacitance.
Data Source
AI summary
An integrated circuit includes a two-dimensional transistor having a channel region having lateral ends in contact with first and second source/drain regions. The transistor includes a gate dielectric that is aligned with the lateral ends of the channel region. The transistor includes a gate metal on the gate dielectric. The gate metal has a relatively small lateral overlap of the first and second source/drain regions.