Self-Aligned 2D Transistor Layout for Short-Channel Control
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Solution Overview
Problem
The challenge of managing short channel effects in transistors as they scale downward, particularly in 2D transistors like 2D TMD and CNT transistors, where traditional source drain doping methods are difficult to implement.
Innovation Solution
The development of an integrated circuit with 2D transistors featuring self-aligned channel regions and gate electrodes, which allows for tightly controlled overlap between the gate electrode and source/drain regions, enabling symmetrical or asymmetrical overlap configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor sizes continue to scale downward to increase computing power, then the number of transistors per area increases, but managing short channel effects becomes very difficult
Solution Approach 1:
The patent introduces a carefully engineered overlap region between the gate electrode and source/drain regions as an intermediary structure. This overlap region, with controlled dimensions and material composition, mediates the interaction between the gate and source/drain, providing better electrostatic control over the channel while maintaining scalability. The overlap acts as a buffer zone that enhances gate control without requiring extreme miniaturization that would lose short channel control.
2Ease of manufacture
If traditional implantation and diffusion methods are used for source drain doping in 2D transistors, then doping can be achieved, but these methods are not available or effective in 2D-TMD and CNT transistors
Solution Approach 1:
The patent changes the fundamental parameters of the doping approach by transitioning from traditional implantation/diffusion methods to in-situ doping or alternative deposition techniques suitable for 2D materials. The source/drain regions are formed with specific material compositions (such as doped semiconducting TMDs or metal contacts) that are deposited using methods compatible with 2D-TMD and CNT structures, thereby adapting the doping process to the unique requirements of two-dimensional transistor materials.
3Reliability
If the gate electrode and source/drain regions have large overlap, then more induced charges are created, but this degrades transistor performance
Solution Approach 1:
The patent applies local quality by creating a spatially varying overlap configuration where the gate electrode overlaps with the source/drain regions in a controlled manner. The overlap dimensions are locally optimized - sufficient to provide necessary electrostatic control and field effect, but limited to minimize excessive induced charges and parasitic capacitance. Different regions of the transistor structure have different overlap characteristics tailored to their specific functional requirements.
4Manufacturing precision
If self-aligned structure is implemented with tightly controlled overlap, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent employs preliminary action through self-aligned fabrication processes where the gate electrode is formed first, and subsequent source/drain regions are deposited in alignment with the gate structure. The overlap configuration is predetermined by the fabrication sequence and material deposition patterns, allowing tight control of overlap dimensions without requiring complex real-time adjustments during manufacturing. The self-alignment mechanism built into the process flow automatically ensures consistent overlap control across devices.
Data Source
AI summary
An integrated circuit includes a two-dimensional transistor having a channel region having lateral ends in contact with first and second source/drain regions. The transistor includes a gate dielectric that is aligned with the lateral ends of the channel region. The transistor includes a gate metal on the gate dielectric. The gate metal has a relatively small lateral overlap of the first and second source/drain regions.