Self-Aligned 3D Conductor E-Fuse for Low-Current Programming
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Solution Overview
Problem
Existing electrical fuses (e-fuses) in semiconductor integrated circuits face challenges in reliable programming, especially in vertical orientations, due to high current requirements and integration difficulties in advanced fabrication processes like replacement metal gate and FinFET configurations, which also consume valuable chip real estate.
Innovation Solution
A self-aligned, sub-lithographic conductor structure is developed, confined in three dimensions by raised structures and dielectric layers, allowing for low current programming and reliable operation across various CMOS configurations, including planar and non-planar FETs, using a method that involves non-conformal dielectric deposition and metal filling to create a conductor that can function as a fuse element.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If vertical e-fuse orientation is used to save chip real estate, then area usage is reduced, but programming reliability deteriorates due to high current requirements and difficulty in achieving precise blow location
Solution Approach 1:
The fuse structure transitions from a planar 2D configuration to a 3D vertically-confined structure. The conductor is positioned within a trench formed between raised structures, creating three-dimensional confinement that enables precise current density control. This dimensional change allows the fuse to achieve reliable programming in the vertical orientation while maintaining compact area footprint.
2Reliability
If horizontal e-fuse orientation is used for reliable programming, then programming reliability is maintained, but chip real estate consumption increases
Solution Approach 1:
Instead of using horizontal orientation to achieve reliable programming, the invention employs vertical orientation with three-dimensional confinement through raised structures and trenches. This dimensional approach enables the fuse to achieve the same programming reliability as horizontal fuses while occupying significantly less chip area.
3Ease of manufacture
If BEOL vertical e-fuse with larger dimensions is used, then integration is simplified, but programming current requirement increases causing blow at undesired locations
Solution Approach 1:
The conductor dimensions are locally optimized within the confined trench structure. The three-dimensional confinement creates a specific geometry where the conductor has controlled cross-sectional area and length, resulting in optimized current density distribution. This local geometric control enables precise blow location at the intended fuse point rather than at adjacent vias or interconnects.
Solution Approach 2:
The transition to 3D confinement within the trench provides an additional degree of freedom for controlling current density. By adjusting the trench dimensions and conductor geometry in three dimensions, the fuse achieves precise blow location control while maintaining compatibility with BEOL integration processes.
4Area of stationary object
If sub-lithographic conductor dimensions are achieved, then area is reduced, but fabrication complexity increases beyond traditional lithography limitations
Solution Approach 1:
The raised structures and trenches are formed in advance before conductor deposition. These pre-formed structures define the sub-lithographic conductor dimensions through their geometry, eliminating the need for direct lithographic patterning of the conductor itself. The conductor is subsequently deposited to fill the pre-defined trench, achieving sub-lithographic dimensions through the preliminary structuring of the surrounding environment.
Solution Approach 2:
The raised structures and trenches serve as intermediary elements that enable sub-lithographic conductor formation. Instead of directly patterning the conductor at sub-lithographic dimensions, the raised structures act as masks and confinement boundaries that define the conductor geometry indirectly, simplifying the fabrication process while achieving the desired sub-lithographic dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables reliable, low-current programming of e-fuses, reduces chip real estate usage, and integrates well with advanced fabrication processes, providing a sub-lithographic feature beyond traditional lithographic limitations.
Implementation Method 1
depositing one or more non-conformal dielectric layers to form a three-dimensional confined region
Implementation Method 2
metal filling to create a conductor that can function as a fuse element
Implementation Method 3
A self-aligned, sub-lithographic conductor structure is developed, confined in three dimensions by raised structures and dielectric layers
Data Source
AI summary
A three-dimensionally (3d) confined conductor advantageously used as an electronic fuse and self-aligned methods of forming the same. By non-conformal deposition of a dielectric film over raised structures, a 3d confined tube, which may be sub-lithographic, is formed between the raised structures. Etching holes which intersect the 3d confined region and subsequent metal deposition fills the 3d confined region and forms contacts. When the raised structures are gates, the fuse element may be located at the middle of the line (i.e. in pre-metal dielectric). Other methods for creating the structure are also described.