Self-Aligned Interconnect Structure With Air Gaps for Via Reliability
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Solution Overview
Problem
As semiconductor industry advances, the increasing aspect ratio of conductive features in dielectric materials in back-end-of-line interconnect structures leads to higher electrical resistivity and RC delay, necessitating improved methods for forming interconnect structures.
Innovation Solution
A dual damascene process is employed, where conductive features are formed simultaneously as part of a conductive layer, with via portions extending upward from bottom portions, and a sacrificial layer is used to create air gaps, reducing electrical resistivity and RC delay by ensuring monolithic and self-aligned structures with controlled shapes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the aspect ratio of conductive features in dielectric material is increased to reduce spacing between components, then device density and functionality are improved, but electrical resistivity and RC delay increase
Solution Approach 1:
The patent introduces air gaps (void spaces) between adjacent conductive features in the interconnect structure. This adds a dimensional element (vertical spacing control) that allows horizontal scaling of conductive features without proportionally increasing spacing requirements, thereby maintaining device density while reducing the effective aspect ratio impact on electrical resistance
Solution Approach 2:
The patent applies different dielectric materials with different properties in different regions: low-k dielectric material is used in specific regions where RC delay is critical, while other dielectric materials are used elsewhere. This localized material selection optimizes electrical performance in high-stress areas without compromising overall device density
2Ease of manufacture
If conventional via formation methods are used, then via structures are created, but voids form and contact landing is poor
Solution Approach 1:
The patent performs preliminary planarization and surface preparation steps before via formation to ensure a flat, uniform surface. This preliminary action prevents void formation during subsequent filling processes and ensures accurate contact landing by establishing a stable baseline for precise via placement and filling
Solution Approach 2:
The patent introduces intermediary layers or materials between the conductive features and underlying structures that facilitate better contact and reduce void formation. These intermediary elements act as mediators that improve the interface quality and ensure reliable electrical connection
Data Source
AI summary
A method for forming an interconnect structure is described. In some embodiments, the method includes forming a conductive layer, removing portions of the conductive layer to form a via portion extending upward from a bottom portion, forming a sacrificial layer over the via portion and the bottom portion, recessing the sacrificial layer to a level substantially the same or below a level of a top surface of the bottom portion, forming a first dielectric material over the via portion, the bottom portion, and the sacrificial layer, and removing the sacrificial layer to form an air gap adjacent the bottom portion.