Self-Aligned Antifuse Via Structure for Low Resistance
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Solution Overview
Problem
Conventional antifuse structures in integrated circuits exhibit high resistance in the on-state, leading to high power consumption and misalignment issues during fabrication due to photolithography and etching processes.
Innovation Solution
The antifuse structure is designed with a self-aligned configuration, where an antifuse layer is deposited within a via that penetrates through an inter-metal dielectric layer, allowing for the self-alignment of electrodes and antifuse layers, reducing misalignment and improving conductivity by forming a conductive path through the deposition of electrodes and interconnect layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional photolithography and etching processes are used to define the antifuse layer, then the antifuse structure can be fabricated, but misalignment between the antifuse layer and electrodes occurs
Solution Approach 1:
The via structure serves itself as the alignment reference for depositing the antifuse layer and electrodes. The antifuse layer is deposited conformally on the via walls and bottom, and electrodes are deposited to fill the via, automatically achieving alignment without requiring separate photolithography patterning steps for the antifuse layer.
Solution Approach 2:
The patent extracts the alignment function from the photolithography process and transfers it to the via structure itself. The via acts as a pre-defined template that guides the subsequent deposition processes, eliminating the need for complex photolithography alignment steps.
2Loss of energy
If conventional antifuse structures are used, then the circuit can be programmed, but high resistance in the on-state results in high power consumption
Solution Approach 1:
The patent optimizes the local quality of the conductive path by carefully controlling the deposition of electrodes and interconnect layers within the via structure. The electrodes are deposited to ensure good electrical contact with the antifuse layer, and the via geometry is optimized to minimize resistance at the interfaces between different layers.
Solution Approach 2:
The antifuse structure uses composite materials including the antifuse layer (dielectric material), electrodes (conductive material), and interconnect layers, where each material is selected and deposited to optimize its specific function while minimizing overall resistance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces the resistance of the antifuse in the on-state, lowering power consumption and enhancing the precision of the antifuse structure fabrication by ensuring accurate alignment of electrodes and antifuse layers, thereby improving the performance of integrated circuits.
Implementation Method 1
An antifuse layer is deposited in the via and over the portion of the first electrode layer
Implementation Method 2
depositing an antifuse layer in the via at least over the portion of the first electrode layer
Implementation Method 3
depositing a conductive material in the via to form a second electrode over the antifuse layer
Implementation Method 4
depositing a second conductive material in the second via to form a second electrode over the antifuse layer
Data Source
AI summary
An antifuse structure includes a first electrode layer, an inter-metal dielectric layer over the first electrode layer, and a via in the inter-metal dielectric layer. The via penetrates through the inter-metal dielectric layer exposing a portion of the first electrode layer. An antifuse layer is deposited in the via and over the portion of the first electrode layer. A second electrode is disposed in the via and over the antifuse layer. An interconnect layer may be deposited over the inter-metal dielectric layer and in electrical contact with the second electrode in the via.