Self-Aligned Auxiliary Layer for Semiconductor Manufacturing
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Solution Overview
Problem
Existing semiconductor manufacturing methods face challenges in achieving seamless contact between monocrystalline and non-monocrystalline layers due to incomplete coverage and edge lag during deposition, leading to poor electrical connections and transistor performance issues, especially in small transistor fabrication.
Innovation Solution
A two-step process is employed to form a self-aligning auxiliary layer, where arsenic is deposited on monocrystalline silicon and a non-monocrystalline silicon layer is formed on silicon oxide, allowing for immediate growth of monocrystalline and non-monocrystalline layers without interference, using arsenic and silicon compounds in controlled atmospheres.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a photoresist mask is used to define active regions and a silicon nitride auxiliary layer is deposited, then the auxiliary layer can be formed on field insulation regions, but aligning tolerances require windows larger than active regions, causing the auxiliary layer to be removed from edges of field insulation regions, resulting in thinner or interrupted monocrystalline layers and poor electrical contact
Solution Approach 1:
The arsenic deposition process automatically defines the auxiliary layer boundaries through self-alignment. The arsenic layer forms only on monocrystalline silicon regions, and the subsequent silicon deposition automatically forms the auxiliary layer only on silicon oxide regions adjacent to the arsenic layer, eliminating the need for photoresist masks and complex alignment procedures
Solution Approach 2:
The arsenic layer serves as an intermediary that defines the boundary between monocrystalline silicon and silicon oxide regions. This intermediary layer enables the subsequent silicon deposition to automatically form the auxiliary layer with precise boundaries without requiring external masking
2Manufacturing precision
If HF etch step is used to clean the surface of active regions before silicon deposition, then the surface is cleaned, but the uncovered edge of field insulation regions is also etched, forming a groove that adversely affects the connection between monocrystalline layer and non-monocrystalline layer
Solution Approach 1:
The arsenic layer automatically protects the edges of field insulation regions during the HF etch step. Since the arsenic layer is present only on monocrystalline silicon regions and the silicon deposition is guided by the arsenic layer boundaries, the HF etch does not create grooves at critical edges, maintaining both surface cleanliness and electrical contact quality
Solution Approach 2:
The arsenic layer is deposited beforehand to prevent unwanted etching or deposition at critical boundaries. This preliminary layer acts as a cushion that protects the edges of field insulation regions from the harmful effects of subsequent processing steps
3Productivity
If deposition is carried out at high temperature to ensure complete monocrystalline growth, then growth is enhanced, but dopant atoms in active regions diffuse, which is undesirable for small transistor manufacture
Solution Approach 1:
The auxiliary layer of non-monocrystalline silicon acts as an intermediary that enhances silicon deposition on silicon oxide regions at low temperatures. This intermediary layer provides nucleation sites that enable complete coverage and monocrystalline growth on monocrystalline silicon regions even at low deposition temperatures, preventing dopant diffusion
Solution Approach 2:
The invention changes the temperature parameter from high to low during silicon deposition. By introducing the auxiliary layer, the process enables complete monocrystalline growth at low temperatures where dopant diffusion is suppressed, thus improving both productivity and manufacturing precision
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method ensures complete coverage and seamless blending of layers, preventing dopant diffusion and enabling low-temperature deposition, resulting in improved transistor performance and reduced edge effects, enhancing the manufacturing of small transistors with precise electrical contacts.
Implementation Method 1
a layer of arsenic is formed on the region of monocrystalline silicon by heating the semiconductor body in an atmosphere with an arsenic compound
Implementation Method 2
a layer of non-monocrystalline silicon is formed as an auxiliary layer on the region of silicon oxide by heating the semiconductor body in an atmosphere comprising a gaseous silicon compound
Implementation Method 3
the monocrystalline and non-monocrystalline layers then deposited blend seamlessly
Data Source
AI summary
Method of manufacturing a semiconductor device, in which on a region of silicon oxide (5) situated next to a region of monocrystalline silicon (4) at the surface (3) of a semiconductor body (1), a non-monocrystalline auxiliary layer (8) is formed. The auxiliary layer is formed in two steps. In the first step, the silicon body is heated in an atmosphere comprising a gaseous arsenic compound; in the second step it is heated in an atmosphere comprising a gaseous silicon compound instead of said arsenic compound. Thus, the regions of silicon oxide are provided with an amorphous or polycrystalline silicon seed layer in a self-aligned manner.