Self-Aligned Backside Contacts for Overlay-Limited Power Delivery
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Forming direct backside contacts (DBC) in semiconductor devices is challenging due to lithography overlay issues and high aspect ratio etch processes, especially as contacted poly pitch becomes smaller, leading to voids and shorts, and the fabrication process is more difficult from the backside of the semiconductor structure.
Innovation Solution
The use of self-aligned backside contact structures, formed using a varying-height silicon germanium stop layer, capping patterns aligned with channel structures, and a backside placeholder element, which are self-aligned based on these patterns, to create a backside contact structure that is electrically connected to source/drain regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If direct backside contacts (DBC) are formed in semiconductor devices, then power delivery effectiveness is improved, but lithography overlay issues and high aspect ratio etch processes cause fabrication difficulties and defects
Solution Approach 1:
The patent applies preliminary action by forming placeholder elements and capping patterns before forming the final backside contact structures. The placeholder elements are formed at the desired contact locations and serve as alignment references for subsequent etching processes. The capping patterns are formed over channel structures to define the precise locations where backside contacts should be formed, ensuring proper alignment without requiring high-precision lithography overlay during the contact formation process itself.
Solution Approach 2:
The patent uses placeholder elements as intermediary structures that facilitate the formation of backside contacts. These placeholders serve as temporary structures that define the contact locations and guide the etching process. The capping patterns also act as intermediaries by providing a reference layer that ensures proper alignment between the backside contacts and the underlying source/drain regions, eliminating the need for complex lithography overlay alignment.
2Power
If direct backside contacts (DBC) are formed with high aspect ratio etch processes, then power delivery effectiveness is improved, but voids and shorts occur due to process difficulties
Solution Approach 1:
The patent performs preliminary actions by forming the placeholder elements and capping patterns before the actual backside contact etching. The placeholder elements pre-define the contact locations and depths, ensuring that the etch process follows a predetermined path that avoids void formation. The capping patterns are formed beforehand to protect channel structures and guide the etching process, preventing shorts between adjacent contacts while ensuring reliable contact formation.
Solution Approach 2:
The placeholder elements serve as intermediary structures that mediate between the etching process and the final contact formation. These placeholders provide a physical template that guides the etch process, ensuring uniform contact depth and shape while preventing void formation. The capping patterns act as intermediaries that protect underlying structures during etching and ensure proper spacing between contacts, thereby preventing shorts and improving overall contact reliability.
3Power
If backside power distribution network is implemented, then voltage drop is reduced and power rail effectiveness is improved, but fabrication complexity increases
Solution Approach 1:
The patent reduces fabrication complexity by performing preliminary actions with placeholder elements and capping patterns that serve as alignment references for all subsequent backside contact formation steps. These preliminary structures are formed once and then used as templates for multiple contacts, eliminating the need for repeated high-precision lithography alignment operations and simplifying the overall fabrication process while enabling the backside power distribution network.
Solution Approach 2:
The placeholder elements and capping patterns serve as intermediary structures that simplify the fabrication process by providing fixed alignment references. These intermediaries decouple the alignment requirements from the actual contact formation step, allowing standard lithography processes to be used without requiring complex overlay control, thereby reducing fabrication complexity while enabling effective backside power distribution networks.
Data Source
AI summary
A method of fabricating a semiconductor device includes forming capping patterns that are spaced apart from each other in a first direction at a first side of a semiconductor structure, and forming channel structures and source/drain regions therebetween that are spaced apart from each other in the first direction at a second side of the semiconductor structure that is opposite the first side of the semiconductor structure. The capping patterns overlap the channel structures in the second direction, respectively. The method further includes forming a backside contact structure that is electrically connected to at least one of the source/drain regions and is aligned to overlap the at least one of the source/drain regions in the second direction based on the capping patterns.