Self-Aligned Backside Gate Contacts for Dual-Side IC Interconnects
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Solution Overview
Problem
Current integrated circuit technologies limit power distribution to the backside of silicon wafers, excluding signal networks, which restricts enhanced system performance, increased chip area utilization, and reduced back-end-of-line (BEOL) complexity.
Innovation Solution
The implementation of self-aligned backside gate contacts enables the integration of signal lines on the backside of integrated circuits, allowing for both power and signal distribution, with backside gate contacts connected to high-K metal gates, facilitating enhanced system performance and reduced BEOL complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If power distribution is moved to the backside of the silicon wafer, then direct power delivery and enhanced system performance are achieved, but signal network integration is excluded and BEOL complexity is not reduced
Solution Approach 1:
The backside of the silicon wafer is designed to support both power distribution and signal network functions through a unified interconnect structure. Power rails and signal lines are integrated on the same backside surface, allowing the backside to serve multiple purposes simultaneously - delivering power directly to devices while also routing control and data signals, thereby achieving both enhanced power delivery and signal network integration
2Ease of manufacture
If both power and signal networks are fabricated on the front side through BEOL processing, then traditional manufacturing is maintained, but chip area utilization is reduced and BEOL complexity increases
Solution Approach 1:
The interconnect network is transitioned from a two-dimensional front-side planar layout to utilize the third dimension by extending to the backside of the wafer. Power rails and signal lines are routed on the backside surface, effectively adding vertical spatial utilization to the interconnect architecture. This dimensional transition increases available routing area, improves chip area utilization, and reduces BEOL processing complexity by separating power/signal routing from the front-side device fabrication
3Manufacturing precision
If backside gate contact vias are formed in STI regions, then self-aligned backside gate contacts are achieved, but additional fabrication steps are required
Solution Approach 1:
Shallow trench isolation (STI) regions are formed between active regions during the front-end-of-line (FEOL) fabrication process, before backside processing begins. These pre-formed STI structures serve as the foundation for subsequent backside gate contact via formation. By preparing the STI infrastructure in advance during FEOL, the backside processing is simplified and requires fewer additional steps while maintaining self-aligned precision
4Manufacturing precision
If dummy gates and gate spacers are formed to fill backside gate contact vias, then self-aligned contact formation is achieved, but process complexity increases
Solution Approach 1:
Dummy gates and gate spacers are formed using self-aligned fabrication techniques where the gate structure itself serves as the alignment reference for contact via formation. The dummy gate material is deposited and patterned to automatically align with the gate position, and gate spacers are formed that self-align to the gate edges. This self-service approach achieves precise self-aligned contact formation while reducing the number of separate alignment steps required
Data Source
AI summary
A semiconductor array structure includes a substrate; a plurality of field effect transistors (FETs) arranged in rows and located on the substrate, each comprising a first source-drain region, a second source-drain region, at least one channel coupling the source-drain regions, and a gate adjacent the at least one channel. A plurality of frontside signal lines are on a front side of the FETs; a plurality of backside power rails are on a back side of the FETs; a plurality of backside signal wires are on the back side. Frontside signal connections run from the frontside signal lines to the first source-drain regions; Power connections run from the backside power rails to the second source-drain regions; and backside gate contact connections run from the backside signal wires to the gates. The backside gate contact connections each have a bottom dimension larger than the gate length.