Self-Aligned Backside Power Rails for Dense FinFET Layouts
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Solution Overview
Problem
Advanced integrated circuits face challenges with shrinking device pitches, shorting, leakage, routing resistance, alignment margins, and packing density due to the scaling down of device sizes, particularly in three-dimensional FinFETs and power rails on the backside of substrates.
Innovation Solution
A semiconductor structure with backside power rails and self-aligned vias is developed, where backside vias connect power rails to device features on fin active regions, and interconnect structures on the front side distribute power, reducing the number of power lines and enhancing routing and processing margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If device sizes are scaled down to increase packing density, then packing density is improved, but alignment margins deteriorate and shorting risk increases
Solution Approach 1:
The patent moves power rail connections from the front side to the back side of the substrate, utilizing the third dimension (substrate thickness) to resolve the conflict between device scaling and alignment precision. Backside power rails are formed through self-aligned processes that eliminate the need for precise overlay alignment, thereby maintaining manufacturing precision while enabling continued device scaling for higher packing density
2Loss of energy
If backside power rails are used to reduce routing resistance, then routing resistance is improved, but shorting and leakage risks worsen
Solution Approach 1:
The backside power rail structure employs self-aligned formation where the power rail is automatically positioned relative to the active regions through the etch stop layer and substrate thinning process. This self-alignment mechanism ensures that power rails are precisely positioned without requiring additional alignment steps, thereby reducing routing resistance while preventing shorting and leakage through accurate positioning
3Ease of operation
If conventional backside power rails are used, then power distribution is achieved, but layout flexibility and routing resistance remain problematic
Solution Approach 1:
The substrate is thinned and an etch stop layer is formed on the back side before power rail formation. This preliminary preparation enables the power rails to be formed with precise control over their position and dimensions, allowing for optimized layout flexibility and reduced routing resistance. The preliminary actions create the conditions necessary for subsequent self-aligned power rail formation
Data Source
AI summary
The present disclosure provides a semiconductor structure that includes a substrate having a frontside and a backside; an active region extruded from the substrate and surrounded by an isolation feature; a gate stack formed on the front side of the substrate and disposed on the active region; a first and a second source/drain (S/D) feature formed on the active region and interposed by the gate stack; a frontside contact feature disposed on a top surface of the first S/D feature; a backside contact feature disposed on and electrically connected to a bottom surface of the second S/D feature; and a semiconductor layer disposed on a bottom surface of the first S/D feature with a first thickness and a bottom surface of the gate stack with a second thickness being greater than the first thickness.