Self-Aligned Backside Power Rails for Overlay-Safe FinFET Scaling
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Solution Overview
Problem
Advanced integrated circuits face challenges with shrinking device pitches, shorting, leakage, routing resistance, alignment margins, layout flexibility, and packing density due to the scaling down of device sizes, particularly in three-dimensional fin transistors and power rails.
Innovation Solution
A semiconductor structure with backside power rails and self-aligned vias is implemented, which includes interconnect structures on the front side to distribute power lines, reducing the number of power lines and increasing space for metal routing, and using silicide to reduce contact resistance, applicable to FinFETs and gate-all-around FETs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing backside power rails are used in advanced technologies, then power distribution is provided, but shorting and leakage issues occur due to shrinking feature sizes and reduced alignment margins
Solution Approach 1:
The patent inverts the conventional approach by forming the backside power rail before forming the transistor structures on the front side. This reverse sequencing allows the power rail to be established as a reference feature, enabling self-aligned formation of contact holes that eliminates overlay errors and prevents shorting between power rails and transistor contacts.
Solution Approach 2:
The backside power rail is formed in advance before the transistor fabrication process begins. This preliminary action creates a fixed reference structure that guides subsequent alignment steps, ensuring that contact holes are automatically positioned correctly relative to the power rail without requiring additional alignment margins.
2Productivity
If feature sizes are shrunk to achieve smaller device pitches, then packing density is improved, but alignment margins are reduced causing shorting and leakage
Solution Approach 1:
By inverting the formation sequence to create power rails first, the patent eliminates the need for alignment margins between power rails and transistor contacts. This enables continuous scaling of feature sizes without compromising alignment reliability, thereby maintaining high packing density while preventing shorting.
3Ease of operation
If front-side metal routing is used for power distribution, then power lines can be distributed, but routing resistance and layout complexity increase
Solution Approach 1:
The patent moves the power rail formation to the backside of the substrate, utilizing the third dimension (substrate thickness) to resolve routing conflicts. This allows power distribution without consuming front-side layout space, reducing routing resistance and simplifying overall layout while maintaining ease of power distribution.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances circuit performance and reliability by reducing routing resistance, improving alignment margins, increasing layout flexibility, and increasing packing density, making it suitable for advanced technology nodes and applications like SRAM cells, logic circuits, and memory devices.
Implementation Method 1
using silicide to reduce contact resistance
Data Source
AI summary
The present disclosure provides a semiconductor structure that includes a substrate having a frontside and a backside; an active region extruded from the substrate and surrounded by an isolation feature; a gate stack formed on the front side of the substrate and disposed on the active region; a first and a second source/drain (S/D) feature formed on the active region and interposed by the gate stack; a frontside contact feature disposed on a top surface of the first S/D feature; a backside contact feature disposed on and electrically connected to a bottom surface of the second S/D feature; and a semiconductor layer disposed on a bottom surface of the first S/D feature with a first thickness and a bottom surface of the gate stack with a second thickness being greater than the first thickness.