Self-Aligned Backside Via Layout for Tight-Pitch Multi-Gate Devices
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Solution Overview
Problem
Existing backside via formation processes for semiconductor devices face challenges in alignment overlay issues leading to electrical shorts and are difficult to implement in devices with reduced pitches, particularly in multi-gate devices like FinFETs and GAA transistors.
Innovation Solution
A method for forming self-aligned backside vias without creating deep trenches in the source/drain regions, involving the formation of shallow trenches, sacrificial semiconductor features, and selective etching to create backside vias, which relaxes photolithography alignment requirements and facilitates scaling down of gate-to-gate pitch.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If existing backside via formation processes are used, then via formation is achieved, but alignment overlay issues occur leading to electrical shorts
Solution Approach 1:
The method performs preliminary actions by forming shallow trenches and sacrificial semiconductor features before backside via formation. These preliminary structures serve as alignment references that guide subsequent via formation, ensuring precise positioning without relying solely on photolithography alignment. The sacrificial features are formed in advance to define the exact locations where vias will be created, preventing misalignment and electrical shorts.
Solution Approach 2:
The patent introduces intermediary structures (shallow trenches and sacrificial semiconductor features) that mediate between the photolithography step and the final via formation. These intermediary elements act as physical references that transfer alignment information from the front side to the back side, eliminating direct alignment dependencies and preventing electrical shorts between vias and gate structures.
2Manufacturing precision
If photolithography alignment requirements are strict, then via placement precision is improved, but process complexity and difficulty increase
Solution Approach 1:
The method employs self-service mechanisms where the shallow trenches and sacrificial semiconductor features automatically define the positions of backside vias through self-aligned formation. The via formation process uses these pre-formed structures as templates, eliminating the need for separate alignment procedures and reducing photolithography stringency requirements while maintaining high placement precision.
3Ease of manufacture
If deep trenches are formed in source/drain regions, then via formation is achieved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent applies local quality by forming shallow trenches only in specific regions where sacrificial semiconductor features are located, rather than forming deep trenches throughout the source/drain regions. This localized approach reduces the overall complexity and manufacturing difficulty while achieving the necessary via formation functionality in the critical areas.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the risk of electrical shorts and enables the formation of backside vias in densely packed multi-gate devices, improving process window and reducing parasitic capacitance.
Implementation Method 1
performing a first etching process to form a trench in the dielectric layer to expose the sacrificial semiconductor feature, performing a second etching process to selectively remove the sacrificial semiconductor feature to vertically extend the trench
Data Source
AI summary
A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary method includes forming a sacrificial feature in a substrate, forming a source/drain feature over the sacrificial feature and protruding from the substrate, planarizing the substrate from its back to reduce its thickness, performing a first etching process to selectively remove the substrate without substantially etching the sacrificial feature, forming a dielectric layer adjacent to and under the sacrificial feature, performing a second etching process to form a trench in the dielectric layer to expose the sacrificial feature, performing a third etching process to selectively remove the sacrificial feature, and forming a conductive feature in the trench.