Self-Aligned BEOL Interconnect Fill for Overlay Error Reduction
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Solution Overview
Problem
Photolithography misalignment in Back End Of the Line (BEOL) metallization leads to patterning defects such as line and vertical interconnect access discontinuities, impacting product reliability and wafer yield due to the narrow patterned features in hard mask layers reducing the alignment window and increasing the risk of overlay errors.
Innovation Solution
A BEOL interconnect fabrication method employing self-aligned patterning and multi-metal gap fill processes, which eliminates the need for a hard mask layer, allowing for wider overlay alignment margins and reducing patterning defects by using conductive materials like graphene and forming dielectric layers with naturally occurring voids to lower the dielectric constant.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If hard mask layer is used for patterning, then precise alignment can be achieved, but the alignment window narrows and patterning defects increase
Solution Approach 1:
The patent removes the hard mask layer from the patterning process entirely, replacing it with a self-aligned approach using spacer structures. This extraction eliminates the source of alignment errors and patterning defects associated with hard mask photolithography, while maintaining precise feature definition through the spacer-based self-aligned method.
Solution Approach 2:
The invention implements self-aligned patterning where the spacer structures automatically define the position of interconnect features relative to the mandrel. This self-service mechanism eliminates the need for separate alignment steps and hard mask layers, as the spacer structures themselves serve as the alignment reference and pattern definition layer.
2Manufacturing precision
If hard mask layer is used for patterning, then pattern definition can be achieved, but process complexity increases
Solution Approach 1:
The patent extracts and removes the hard mask layer and associated photolithography alignment steps from the patterning process. This simplification reduces the number of process steps and materials required, while the spacer-based self-aligned approach maintains accurate pattern definition through a more streamlined process flow.
Solution Approach 2:
The invention merges the functions of the hard mask layer and alignment reference into the spacer structures themselves. The spacers simultaneously serve as the pattern definition layer and the alignment reference for subsequent etching steps, eliminating the need for separate hard mask and alignment layers, thus reducing overall process complexity.
3Reliability
If dielectric layer with voids is formed, then dielectric constant is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent incorporates voids or pores within the dielectric layer structure to reduce the effective dielectric constant. This porous dielectric material lowers the capacitance between interconnect lines, improving signal integrity and reducing RC delays, while the voids are integrated into the dielectric formation process through controlled deposition or infiltration techniques.
Data Source
AI summary
Photolithography overlay errors are a source of patterning defects, which contribute to low wafer yield. An interconnect formation process that employs a patterning photolithography/etch process with self-aligned interconnects is disclosed herein. The interconnection formation process, among other things, improves a photolithography overlay (OVL) margin since alignment is accomplished on a wider pattern. In addition, the patterning photolithography/etch process supports multi-metal gap fill and low-k dielectric formation with voids.