Self-Aligned Active Regions and Passivation for BEOL Transistors
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Solution Overview
Problem
Conventional transistors face challenges in precisely controlling the formation of N+ doped regions and protecting the channel region from degradation due to processing conditions and ambient gases during BEOL integration.
Innovation Solution
The implementation of self-aligned active regions and a self-aligned passivation layer in field effect transistors, which are formed over the channel layer and line the contact via structures, respectively. This approach aids in precise doping and protects the channel region from environmental degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional transistor fabrication is used, then manufacturing process is simpler, but precision in forming N+ doped regions and protecting channel region deteriorates
Solution Approach 1:
A metal layer is deposited over the channel layer and patterned contact via structures before doping. This metal layer serves as a preliminary structure that defines the precise location where N+ doped regions will form through subsequent annealing, enabling accurate positioning without complex alignment steps
Solution Approach 2:
The metal layer acts as an intermediary between the doping process and the channel layer. During annealing, this metal layer reacts with the channel layer to form N+ doped regions at precise locations, while also serving as a mask to protect surrounding areas, thereby achieving high precision without complex fabrication steps
2Reliability
If conventional transistor fabrication is used, then manufacturing process is simpler, but protection of channel region from degradation deteriorates
Solution Approach 1:
A passivation layer is deposited over the channel layer and patterned contact via structures before final transistor fabrication. This preliminary passivation layer protects the channel region from degradation by ambient gases and processing conditions during subsequent BEOL integration steps
Solution Approach 2:
The passivation layer serves as an intermediary protective barrier between the channel layer and the harsh processing environment. It prevents direct exposure of the channel region to degrading factors while allowing the doping process to proceed through controlled interaction with the metal layer
3Area of stationary object
If transistors are made smaller to increase areal density, then chip area utilization improves, but control over doping and protection deteriorates
Solution Approach 1:
The metal layer and passivation layer are deposited as continuous films that automatically conform to the underlying topography of the channel layer and contact via structures. This self-aligned deposition process eliminates the need for separate alignment steps, maintaining high precision even as transistor dimensions are reduced to increase areal density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables precise control over the formation of N+ doped regions and effectively protects the channel region, enhancing the reliability and performance of transistors integrated in the BEOL.
Implementation Method 1
annealing the metal layer in direct contact with the patterned channel layer to form active regions that are self-aligned to the contact via structures
Implementation Method 2
a self-aligned passivation protection layer that lines the contact via structures and protects the channel region from degradation
Data Source
AI summary
Field effect transistors and method of making. The field effect transistor includes a pair of active regions over a channel layer, a channel region formed in the channel layer and located between the pair of active regions, a pair of contact via structures electrically connected to the pair of active regions, and a lower passivation protection layer. The lower passivation protection layer extends over a top surface of an end portion of the channel layer, a side surface of the end portion of the channel layer, and a side surface of a gate dielectric layer disposed under the channel layer.