Self-Aligned BEOL Vias for Precise Metal Line Integration
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Solution Overview
Problem
The challenge in semiconductor manufacturing lies in achieving precise alignment of vias with underlying electrically conductive structures, particularly at small pitches and critical dimensions, which leads to increased BEOL resistance-capacitance delays and reduced reliability due to misalignment.
Innovation Solution
A method for manufacturing self-aligned vias in the BEOL using direct metal etch techniques, ensuring alignment with both top and bottom metal lines, thereby reducing misalignment and improving reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional via alignment methods are used, then manufacturing process is simpler, but via alignment precision deteriorates leading to increased RC delays
Solution Approach 1:
The patent applies preliminary action by forming a mandrel structure before the via etch process. The mandrel is deposited and patterned to define the exact via location, ensuring self-alignment with the underlying conductive structure. This preliminary mandrel formation enables precise via placement without requiring complex alignment steps during the actual via fabrication process.
Solution Approach 2:
The patent introduces a mandrel as an intermediary structure that mediates between the patterning layer and the via etch process. The mandrel serves as a temporary structure that defines the via opening location and shape, enabling precise alignment while simplifying the overall manufacturing process by decoupling the alignment function from the via formation steps.
2Manufacturing precision
If via size is reduced to increase density, then device capacity increases, but alignment precision becomes more critical and harder to achieve
Solution Approach 1:
The mandrel structure is formed in advance with precise dimensions and positioning, enabling small via sizes to be achieved with high alignment precision. The mandrel's pre-formed geometry ensures that even at reduced via dimensions, the alignment with underlying conductive structures remains accurate, thus supporting increased device density without sacrificing precision.
Solution Approach 2:
The patent changes the physical parameters of the via formation process by using a mandrel-defined etch approach. This allows precise control of via dimensions and positioning, enabling scaling to smaller via sizes while maintaining alignment precision through the mandrel's geometric constraints and material properties.
3Reliability
If misalignment between vias and underlying structures occurs, then manufacturing is easier, but reliability deteriorates due to increased RC delays
Solution Approach 1:
The mandrel structure enables self-alignment of vias with the underlying conductive structures. The mandrel is positioned and dimensioned to automatically define the correct via location, eliminating the need for complex alignment procedures. This self-aligning mechanism ensures high reliability through precise via placement while maintaining ease of manufacture by simplifying the formation process.
Data Source
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AI summary
Disclosed herein are methods for manufacturing an integrated circuit (IC) structure, e.g., for manufacturing a metallization stack portion of an IC structure, with one or more self-aligned vias integrated in the back end of line (BEOL), and related semiconductor devices. The methods may employ direct metal etch for scaling the BEOL pitches of the metallization layers. In one aspect, an example method results in fabrication of a via that is self-aligned to both a metal line above it and a metal line below it. Methods described herein may provide improvements in terms of one or more of reducing the misalignment between vias and electrically conductive structures connected thereto, reducing the RC delays, and increasing reliability if the final IC structures.