Self-Aligned Bit Line Contact Structure for Embedded Memory
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Solution Overview
Problem
As semiconductor devices transition to nanometer technology process nodes, the complexity of three-dimensional designs increases, making traditional bit line contact formation processes cumbersome and costly, affecting production yield and device reliability.
Innovation Solution
The implementation of a self-aligned bit line structure that integrates a contact surface directly on the bit line, eliminating the need for separate bit line contact formation sequences, thereby simplifying the manufacturing process and improving yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional bit line contact formation processes are used, then separate contact formation steps can be performed, but manufacturing complexity increases and production yield decreases
Solution Approach 1:
The patent merges the bit line contact formation with the bit line structure formation by creating a self-aligned contact during the bit line deposition process itself. The contact is formed as an integrated part of the bit line structure through selective etching and filling, eliminating the need for separate contact formation steps and reducing overall manufacturing complexity
Solution Approach 2:
The bit line structure serves its own contact formation function through self-alignment mechanisms. The contact is automatically positioned and formed as part of the bit line fabrication process, where the bit line structure itself defines the contact location and geometry, eliminating the need for additional dedicated contact formation processes
2Reliability
If separate bit line contact formation sequences are used, then contacts can be formed independently, but production yield decreases and costs increase
Solution Approach 1:
The patent combines multiple functions into a single integrated process where bit line formation and contact formation occur simultaneously. This merging reduces the number of process steps from multiple sequential operations to a unified process, thereby improving production yield while maintaining device reliability through self-aligned precision
Solution Approach 2:
The contact structure is prepared in advance as part of the bit line formation process. The self-aligned contact is pre-formed during bit line deposition and patterning, ensuring proper alignment and reducing subsequent processing requirements, which improves both yield and reliability
3Ease of manufacture
If traditional contact formation methods are used, then contacts can be formed with separate processing, but additional processing steps and costs are required
Solution Approach 1:
The patent merges contact formation with bit line fabrication into a single process flow. By forming the contact as an integrated feature during bit line deposition and patterning, the method eliminates separate contact formation steps, reducing both processing time and manufacturing costs while maintaining ease of manufacture
Data Source
AI summary
A method of manufacturing an integrated circuit includes depositing a first dielectric layer having a thickness TD1. The method further includes patterning and etching the first dielectric layer to form a primary recess having a sidewall depth DR1, a recess width WR1, and a recess length LR1. The method further includes depositing a first conductive layer having a thickness TC1 in the primary recess, a residual portion of the primary recess forming a secondary recess. The method further includes depositing a second dielectric layer in the secondary recess. The method further includes planarizing the integrated circuit to form a planar surface with a residual portion of the first conductive layer forming a first conductive structure within the primary recess. The first conductive structure includes a horizontal portion and a vertical portion, and a first contact surface of the vertical portion is exposed on the planar surface.