Self-Aligned Vertical Bitlines for Low-Resistance 3D DRAM
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Solution Overview
Problem
Three-dimensional dynamic random-access memory (DRAM) devices face challenges in manufacturability due to their 3D designs and small sizes, leading to high parasitic resistance in vertical bit lines formed through conventional high-aspect-ratio etching processes, which result in voids and increased resistance.
Innovation Solution
The formation of vertical metal bit lines using a selective self-aligning deposition process with metal silicide interfaces, eliminating the need for high-aspect-ratio etching and reducing parasitic resistance by providing an ohmic contact between the FET device and the bit lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If high-aspect-ratio etching process is used to form vertical bit lines, then bit lines can be formed in 3D structure, but voids are created leading to high parasitic resistance
Solution Approach 1:
The patent replaces the mechanical etching process with a chemical deposition process. Instead of using physical etching to create vertical bit line slots, the invention uses selective chemical vapor deposition to directly form metal silicide bit lines on the semiconductor layer surfaces, eliminating the void formation problem associated with etching.
Solution Approach 2:
The patent changes the material parameter from conventional metal to metal silicide, and changes the formation process parameter from etching to selective deposition. This parameter change enables direct formation of continuous, void-free vertical bit lines with lower parasitic resistance.
2Ease of operation
If conventional etching and filling process is used, then vertical bit lines can be formed, but multiple process steps are required increasing complexity
Solution Approach 1:
The patent merges multiple process steps into a single selective deposition process. The formation of bit lines, interfaces, and contacts is combined into one step where metal silicide is selectively deposited on semiconductor surfaces, eliminating the need for separate etching, filling, and interface formation steps.
Solution Approach 2:
The selective deposition process is self-aligning, where the metal silicide automatically forms only on the semiconductor layer surfaces and not on the spacer or other structures. This self-service characteristic eliminates the need for additional alignment and patterning steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces parasitic resistance and improves the manufacturability of 3D DRAM devices by forming continuous metal bit lines with minimized voids, enhancing the performance and reliability of the memory cells.
Implementation Method 1
performing a first selective deposition process to form a metal silicide layer selectively on a sidewall of a trench, the sidewall of the trench comprising a first cross section of each of a plurality of semiconductor layers
Data Source
AI summary
A semiconductor structure includes a plurality of memory levels stacked in a first direction, each of the plurality of memory levels including a semiconductor layer, a word line metal layer, and an interface on a cross section of the semiconductor layer, a spacer between adjacent memory levels of the plurality of memory levels in the first direction, and a bit line in contact with the interface of each of the plurality of memory levels, the bit line extending in the first direction. The bit line comprises metal material, and the interface comprises silicide.