Self-Aligned Body Transistor for Low Rdson and High BVdss
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor devices face challenges in achieving low on-resistance (Rdson) and high drain-to-source breakdown voltage (BVdss) while minimizing gate charge (Qgg), which are crucial for high performance and reliability, especially in high voltage applications.
Innovation Solution
The method involves forming a transistor with a self-aligned body and under-lap portion beneath the gate, using specific doping regions and isolation wells to optimize the channel length and reduce Rdson, and employing a salicide block spacer to increase the effective drift region length and reduce Cgd, allowing for a narrower gate width with higher BVdss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the channel length is reduced to achieve low Rdson, then the on-resistance decreases, but the drain-to-source breakdown voltage BVdss also decreases
Solution Approach 1:
The patent introduces a vertical drift well structure beneath the gate that extends into the substrate, adding a vertical dimension to the voltage blocking path. This allows the horizontal channel length to be shortened for low Rdson while the vertical drift region maintains high BVdss through its extended depth and controlled doping profile.
Solution Approach 2:
The device structure is segmented into distinct functional regions: a horizontal channel region for current conduction, a vertical drift well for voltage blocking, and a body region for carrier generation. This segmentation allows each region to be independently optimized for its specific function, enabling low Rdson in the channel while maintaining high BVdss in the drift well.
2Quantity of substance
If the gate width is reduced to achieve low Qgg, then the gate charge decreases, but the current carrying capacity and Rdson increase
Solution Approach 1:
The patent compensates for reduced gate width by extending the drift well vertically beneath the gate. This vertical extension increases the effective area for voltage blocking and current conduction without increasing the horizontal gate footprint, thereby maintaining low Qgg while preventing Rdson from increasing.
Solution Approach 2:
The patent changes the doping parameters in the drift well, using high concentration dopants (1E19 to 1E21 atoms/cm³) at specific depths to create a highly conductive vertical path. This allows the device to achieve low Rdson through enhanced vertical conduction rather than relying solely on increased gate width.
3Reliability
If the drift region length is increased to achieve high BVdss, then the breakdown voltage increases, but the device area and capacitance increase
Solution Approach 1:
The patent transitions from a lateral drift region to a vertical drift well structure. This vertical orientation achieves the required BVdss through increased depth rather than lateral extension, significantly reducing the device footprint while maintaining high breakdown voltage capability.
Solution Approach 2:
The drift well is doped with locally optimized concentration profiles, using high dopant concentrations (1E19 to 1E21 atoms/cm³) in specific depth ranges to maximize voltage blocking efficiency per unit depth. This local optimization reduces the required drift well depth compared to uniform doping, thereby reducing device area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in lower Rdson and Qgg, enabling higher performance, reliability, and flexibility in voltage applications, with achievable BVdss of greater than 15 V and Rdson of less than 5 mOhm-mm² for a range of voltage applications.
Implementation Method 1
Second polarity type dopants are implanted into the substrate in a first side of the gate to form a body within the drift well. The implant is self-aligned to the gate.
Implementation Method 2
First and second diffusion regions having first polarity type dopants are formed in the substrate in the device region adjacent to the first and second sides of the gate
Data Source
AI summary
A device having a self-aligned body on a first side of a gate is disclosed. The self-aligned body helps to achieve very low channel length for low Rdson. The self-aligned body is isolated, enabling to bias the body at different bias potentials. The device may be configured into a finger architecture having a plurality of transistors with commonly coupled, sources, commonly coupled gates, and commonly coupled drains to achieve high drive current outputs.