Self-aligned borderless contacts using sacrificial carbon layer
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Solution Overview
Problem
The challenge in semiconductor technology is the misalignment of source and drain contacts with respect to the gate, leading to electrical shorts and rendering devices inoperable, particularly as integration density increases with technology scaling.
Innovation Solution
A method for fabricating self-aligned borderless electrical contacts using a gate stack with an off-set spacer, sacrificial carbon-based film, and selective patterning to define contact areas, allowing for self-alignment and relaxed dimensional specifications without compromising device functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithographic techniques are used to form contacts at high integration density, then manufacturing complexity increases and alignment precision deteriorates, leading to electrical shorts
Solution Approach 1:
The method performs preliminary patterning of the sacrificial layer to define contact openings before forming the actual contacts. This preliminary action establishes precise contact locations that self-align with gate and source/drain regions, eliminating alignment issues that would otherwise require complex multi-step lithographic processes at high integration density
Solution Approach 2:
A sacrificial layer is introduced as an intermediary material that temporarily occupies the contact opening locations. This intermediary enables simplified lithographic patterning while ensuring precise contact alignment, as the sacrificial layer can be patterned with conventional techniques and then removed to reveal self-aligned contact openings
2Productivity
If contact pitch is reduced for higher integration density, then alignment tolerance decreases and risk of electrical shorts increases
Solution Approach 1:
The contact alignment is achieved through self-service mechanisms where the sacrificial layer patterning and subsequent contact formation automatically self-align with the gate and source/drain regions. This self-alignment process eliminates the need for tight alignment tolerances, enabling reduced contact pitch and higher integration density without increasing electrical short risk
3Ease of manufacture
If borderless contacts are formed with relaxed dimensional specifications, then manufacturing ease improves, but contact definition precision must be maintained
Solution Approach 1:
The method extracts the alignment-critical dimensions from the contact formation process by using the sacrificial layer to define contact openings. This allows the actual contacts to be formed with relaxed dimensional specifications while maintaining precise contact area definition, as the sacrificial layer pattern (not the contact dimensions themselves) determines the critical alignment geometry
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of borderless contacts that meet the demands of high-density electronic and memory device scaling, allowing for efficient contact formation with conventional lithographic techniques and improved alignment, reducing the risk of electrical shorts.
Implementation Method 1
reacting the metal with the Si by a rapid thermal annealing process
Implementation Method 2
The sacrificial layer that has been patterned is selectively removed exposing the contact areas
Data Source
AI summary
A method for fabricating a transistor having self-aligned borderless electrical contacts is disclosed. A gate stack is formed on a silicon region. An off-set spacer is formed surrounding the gate stack. A sacrificial layer that includes a carbon-based film is deposited overlying the silicon region, the gate stack, and the off-set spacer. A pattern is defined in the sacrificial layer to define a contact area for the electrical contact. The pattern exposes at least a portion of the gate stack and source/drain. A dielectric layer is deposited overlying the sacrificial layer that has been patterned and the portion of the gate stack that has been exposed. The sacrificial layer that has been patterned is selectively removed to define the contact area at the height that has been defined. The contact area for the height that has been defined is metalized to form the electrical contact.