Self-Aligned Bottom Spacer Layout for Uniform Vertical Transistors
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Solution Overview
Problem
Current manufacturing processes for vertical transistors result in undesirable device-layout and feature-related variations in bottom spacers, leading to inconsistent performance due to the loading effect, where closely spaced transistors may have thinner bottom spacers compared to those that are more widely separated.
Innovation Solution
A method involving the formation of vertical fins with conformal spacers, followed by isotropic selective etching to create uniform bottom spacers, and the subsequent formation of a shallow-trench-isolation (STI) structure with a T-shape that covers and isolates the bottom spacers, ensuring consistent spacer width regardless of transistor spacing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional bottom spacer manufacturing process is used, then transistors can be manufactured with standard process flow, but bottom spacers exhibit layout-related variations in thickness leading to performance inconsistency
Solution Approach 1:
The patent applies preliminary action by forming the conformal spacer layer on the substrate and fins before any patterning or etching steps. This conformal layer serves as a pre-prepared uniform foundation that will later define the bottom spacer thickness, ensuring that the spacer thickness is determined by the conformal deposition process rather than subsequent lithography or etching variations.
Solution Approach 2:
The patent implements self-service through the self-aligned etching process where the conformal spacer layer automatically defines the etch stop position. The isotropic etch removes material until it hits the conformal spacer, which serves as its own etch stop, eliminating the need for separate alignment marks or complex photolithography steps to define spacer boundaries.
2Productivity
If transistors are placed closely together to increase device density, then footprint is reduced, but loading effect causes bottom spacers to become thinner in closely spaced transistors
Solution Approach 1:
The patent applies local quality by making the bottom spacer thickness independent of the local transistor spacing environment. The conformal spacer layer provides a uniform thickness across the entire wafer regardless of whether transistors are closely spaced or widely separated, eliminating the loading effect that previously caused thickness variations based on local density.
Solution Approach 2:
The patent changes the fundamental parameter used to define spacer thickness from a lithography-based dimensional control to a conformal deposition thickness control. By using atomic layer deposition or chemical vapor deposition to form the conformal spacer layer, the thickness is controlled by deposition time and rate rather than by optical lithography resolution, making it insensitive to transistor spacing variations.
3Device complexity
If standard spacer formation process is used, then manufacturing process is simpler, but feature-related variations cause inconsistent spacer dimensions
Solution Approach 1:
The patent uses preliminary action by depositing the conformal spacer layer as a pre-patterned structure before any transistor-specific processing. This conformal layer is formed uniformly across the entire substrate, establishing a consistent spacer thickness baseline that applies to all transistors regardless of their specific layout or size, thereby reducing feature-related variations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures that bottom spacers have a uniform vertical thickness, eliminating device-layout and pattern-related variations, thereby enhancing the performance consistency of vertical transistors by maintaining spacer width uniformity across different transistor configurations.
Implementation Method 1
indenting the conformal spacer includes performing an isotropic selective etching process to remove portions of the conformal spacer between the sidewall spacers and the substrate to expose a bottom portion of the set of vertical fins
Implementation Method 2
the STI structure isolates the first bottom S/D region of the first vertical transistor from the second bottom S/D region of the second vertical transistor
Data Source
AI summary
Embodiments of present invention provide a method of forming a transistor structure. The method includes forming a set of vertical fins on top of a substrate; forming a conformal spacer lining the set of vertical fins and the substrate; forming sidewall spacers next to vertical portions of the conformal spacer; removing portions of the conformal spacer on top of the substrate and between the sidewall spacers; indenting the conformal spacer vertically between the sidewall spacers and the substrate to create openings; forming bottom spacers in the openings; and forming a shallow-trench-isolation (STI) structure between the bottom spacers. A structure formed thereby is also provided.