Self-Aligned Bridge Via Patterning for Backside Interconnect Scaling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current backside interconnect patterning for power vias in semiconductor devices is complex, costly, and prone to variations, making it challenging for future process nodes with increased device density and smaller patterning spaces.
Innovation Solution
A self-aligned via patterning process that eliminates the need for multiple lithography operations by using material selection, etch and polish selectivity, and patterning sequencing, allowing for thinner insulative liners and improved transistor density and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If advanced lithography steps are used for power via patterning, then patterning precision is improved, but process complexity and cost increase
Solution Approach 1:
The patent implements self-aligned patterning where the insulative liner is deposited conformally on the via structure, and the via opening is automatically defined by the etch stop layer pattern. This self-alignment mechanism eliminates the need for separate lithography alignment steps, reducing process complexity while maintaining patterning precision through the inherent alignment of the self-aligned process
Solution Approach 2:
The etch stop layer is deposited and patterned in advance before via formation. This preliminary patterning establishes the via opening locations and dimensions before the actual via etching, allowing subsequent steps to be self-aligned and reducing the need for additional lithography operations
2Manufacturing precision
If multiple lithography operations are used for power via patterning, then patterning precision is improved, but manufacturing cost increases
Solution Approach 1:
The patent combines multiple patterning functions into a single lithography step. The etch stop layer pattern simultaneously defines the via openings and serves as the alignment reference for the insulative liner deposition, merging what would traditionally require separate lithography operations into one step, thereby reducing manufacturing cost while maintaining precision
Solution Approach 2:
The etch stop layer serves multiple functions: it acts as a pattern definition layer for via openings, an etch barrier during via formation, and an alignment reference for subsequent insulative liner deposition. This multi-functionality eliminates the need for separate dedicated patterning layers and lithography steps, reducing overall manufacturing cost
3Adaptability or versatility
If current patterning schemes are used for power vias, then existing process compatibility is maintained, but yield and performance are adversely impacted due to marginality and variation issues
Solution Approach 1:
The self-aligned patterning mechanism inherently compensates for process variations by automatically aligning the insulative liner to the via opening through conformal deposition on the etch stop layer. This self-alignment eliminates marginality issues associated with multi-step lithography alignment, improving yield and performance while maintaining compatibility with existing process flows
Solution Approach 2:
The etch stop layer is deposited with sufficient thickness to serve as both a pattern definition and an etch barrier. This preliminary cushioning layer provides process margin against etch depth variations and alignment tolerances, preventing yield loss from marginality issues while working within existing process capabilities
4Productivity
If device density is increased for future process nodes, then transistor performance is improved, but patterning space becomes significantly smaller making current techniques non-extensible
Solution Approach 1:
The self-aligned patterning approach requires minimal lateral patterning space because the insulative liner is automatically positioned by conformal deposition on the via structure. This eliminates the need for large alignment margins and process windows that would be required for multi-step lithography, making the technique extensible to future high-density nodes where patterning space is constrained
Solution Approach 2:
The patent transitions from lateral patterning parameters (lithography resolution, alignment margins) to vertical structure parameters (etch stop layer thickness, conformal deposition uniformity). This parameter change enables scaling to smaller dimensions because vertical control is more precise and less sensitive to density increases than lateral patterning
Data Source
AI summary
Devices, transistor structures, systems, and techniques are described herein related to coupling backside and frontside metallization layers that are on opposite sides of a device layer. A device includes a transistor having semiconductor structures extending between a source and a drain, and a gate between the source and drain, a bridge via extending between a frontside metallization over the transistor and a backside metallization below the transistor, and a thin insulative liner between the bridge via and components of the transistor.