Self-Aligned Buried Power Rails for Sub-6T Track Scaling
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Solution Overview
Problem
In semiconductor device fabrication, reducing the track count of power rails beyond 6T is challenging due to limited signal tracks and lithographic overlay tolerances, making it difficult to bury power rails without shorting devices, especially in smaller technology nodes.
Innovation Solution
The method involves forming fin structures of different dimensions, creating trenches, and filling them with conductive metal to form self-aligned buried power rails, which are aligned with neighboring fins to reduce variability and increase process window margin, using techniques like self-aligned quadruple patterning and high-melting point metals like Ru or W.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If power rails are buried in smaller technology nodes to reduce track count, then area scaling is improved, but device shorting risk increases due to lithographic overlay tolerances
Solution Approach 1:
The power rail structure uses self-aligned fin formations where the fins themselves define the boundaries of the power rail trenches. This self-alignment mechanism eliminates the need for separate alignment processes, ensuring precise positioning that prevents device shorting while enabling buried power rails in scaled technology nodes
Solution Approach 2:
The method forms fins of different dimensions in advance before creating the power rail trenches. By pre-forming the dimensional references (different fin heights), the subsequent trench formation and power rail embedding are automatically aligned, preventing shorting before the actual power rail formation occurs
2Area of stationary object
If track count is reduced beyond 6T to improve area scaling, then device density is improved, but signal track availability for automated routing deteriorates
Solution Approach 1:
The invention moves power rail connections from the lateral plane (track level) to the vertical dimension by burying power rails beneath active device regions. This dimensional transition frees up lateral signal tracks for routing while maintaining power delivery through vertical fin and trench structures
3Area of stationary object
If power rail width is tightened to improve area scaling, then area efficiency is improved, but resistance and capacitance variability increases
Solution Approach 1:
The self-aligned fin structure automatically defines the power rail trench width based on the fin dimensions themselves. This self-defining mechanism ensures consistent trench width and power rail dimensions, reducing variability in resistance and capacitance while maintaining tight area scaling
Solution Approach 2:
By pre-forming fins with controlled dimensions before trench formation, the method establishes precise geometric references that guide subsequent power rail fabrication. This preliminary dimensional control ensures consistent power rail width and electrical characteristics across the device
Data Source
AI summary
The present disclosure relates to semiconductor structures and, more particularly, to self-aligned buried power rail structures and methods of manufacture. The method includes: forming at least one fin structure of a first dimension in a substrate; forming at least one fin structure of a second dimension in the substrate; removing at least a portion of the at least one fin structure of the second dimension to form a trench; filling the trench with conductive metal to form a buried power rail structure within the trench; and forming a contact to the buried power rail structure.