Self-Aligned Channel Cap Structure for 3D Memory Openings

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Solution Overview

Problem

Current three-dimensional memory devices face challenges in forming self-aligned channel cap structures efficiently, which are crucial for enhancing memory density and performance, due to limitations in existing fabrication methods.

Innovation Solution

A semiconductor structure and method involving an alternating stack of insulating and electrically conductive layers, where memory openings are formed with a semiconductor core and annular cap structures, allowing for the formation of vertical semiconductor channels and source layers with precise control over p-n junctions, reducing the need for additional processing steps and thermal budgets.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional fabrication methods are used to form channel cap structures, then additional processing steps and thermal budgets are required, but this increases fabrication complexity and adversely affects copper interconnects and bonding pads

Engineering Contradiction:
Improvecontrol of p-n junctionsVSAvoidfabrication process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The semiconductor cap structure is formed preliminarily during the memory opening formation process, before the vertical semiconductor channels are created. This preliminary formation of the cap structure on the memory opening sidewalls eliminates the need for subsequent separate processing steps to form channel cap structures, thereby reducing fabrication complexity while maintaining precise control over p-n junctions

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The semiconductor cap structure is nested within the memory opening, forming an integrated structure that combines the cap formation with the memory opening formation process. This nesting approach allows the cap structure to be formed as part of the existing process sequence without requiring additional thermal budgets or separate fabrication steps

Inventive Principle:
Principle #7Nested doll (Nesting)

2Manufacturing precision

If additional processing steps are added to form self-aligned channel cap structures, then p-n junction control is improved, but fabrication time and thermal budget increase

Engineering Contradiction:
Improvep-n junction alignmentVSAvoidfabrication time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

The formation of the semiconductor cap structure is merged with the memory opening formation process. The cap structure is formed as an integrated part of the memory opening fabrication sequence, combining multiple functions into a single process flow that achieves self-alignment without requiring additional time-consuming steps

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The cap structure is formed preliminarily during the memory opening formation process, establishing the self-aligned configuration before vertical semiconductor channels are created. This preliminary action ensures precise p-n junction alignment while avoiding the need for subsequent alignment-critical processing steps

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20240407164A1Three-dimensional memory devices including self-aligned channel cap structures and methods for forming the same
Publication Date: 2024.12.05 SANDISK TECHNOLOGIES LLC
  • US20240407164A1 patent drawing
  • US20240407164A1 patent drawing
  • US20240407164A1 patent drawing

AI summary

A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, a memory opening fill structure located in the memory opening and comprising a memory film, a vertical semiconductor channel, and a semiconductor cap structure that includes a semiconductor core structure contacting a bottom end of the vertical semiconductor channel and an annular semiconductor structure laterally surrounding the semiconductor core structure and having a lesser vertical extent than the semiconductor core structure, and a source layer contacting a bottom surface of the semiconductor core structure.