Self-Aligned Contact Cap for Semiconductor Gate Structures

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

In semiconductor processing, the formation of contacts over gate conductors can lead to shorting issues due to erosion of dielectric caps during contact hole etching, and seams within the metal fill material pose a risk of device failure.

Innovation Solution

A method involving recessing the gate conductor to form a first divot, creating a gate cap, and then expanding a dielectric fill to form a profile growth layer that creates a second divot, allowing for the formation of a top cap with sufficient thickness to prevent interaction with seams and ensure adequate protection during contact formation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If dielectric caps are formed over gate conductors to prevent shorting, then shorting prevention is improved, but the caps are eroded away during contact hole etching causing shorting concerns

Engineering Contradiction:
Improveshorting preventionVSAvoidcap thickness retention
Core Design Contradiction:
ReliabilityVSDuration of action of stationary object

Solution Approach 1:

The cap structure is divided into multiple segments: a first dielectric cap formed initially, then after recessing the gate conductor and forming a profile growth layer, a second dielectric cap is formed. This segmented approach allows the first cap to provide initial protection while the second cap provides enhanced protection against erosion during contact hole etching, resolving the contradiction between preventing shorting and maintaining cap thickness.

Inventive Principle:
Principle #1Segmentation

2Reliability

If gate conductor is recessed deeply to avoid seams, then seam interaction is prevented, but contact hole etching becomes more difficult and process tolerance is reduced

Engineering Contradiction:
Improveseam avoidanceVSAvoidcontact formation complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

A profile growth layer is introduced as an intermediary structure between the gate conductor and the contact hole etch process. This layer is formed by expanding a dielectric material in a divot region, creating a tapered profile that guides the etch process and prevents direct interaction with seams while maintaining process tolerance. The intermediary layer resolves the contradiction by providing a buffer zone that simplifies contact formation.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If a thick cap is formed to provide process tolerance, then etch protection is improved, but the formation process becomes more complex with additional steps

Engineering Contradiction:
Improveetch protectionVSAvoidcap formation process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The first dielectric cap is formed preliminarily before the gate conductor is recessed and before the profile growth layer is created. This preliminary cap provides initial protection and serves as a foundation for subsequent processing steps. The preliminary action allows for a more manageable multi-step process where each step builds upon the previous one, resolving the contradiction between providing thick cap protection and maintaining process simplicity.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach provides increased process tolerance and prevents the recess from exposing seams, maintaining a sufficient dielectric thickness to prevent shorting and ensure reliable contact formation.

Implementation Method 1

The extension layer is expanded to form a profile growth layer that is thicker than the extension layer

Methodology Applied
Scientific EffectOxidation: Oxidation

Data Source

PatentUS10985062B2Self-aligned contact cap
Publication Date: 2021.04.20 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US10985062B2 patent drawing
  • US10985062B2 patent drawing
  • US10985062B2 patent drawing

AI summary

A method for forming a semiconductor device includes recessing a gate conductor in a gate structure to form a first divot, forming a gate cap in the first divot and recessing a dielectric fill that encapsulates the gate structures to a position below a top of the gate cap. An extension layer is deposited over the dielectric fill and the top of the gate cap and is planarized to the top of the gate cap. The extension layer is expanded to form a profile growth layer that is thicker than the extension layer and creates a second divot over the gate cap. A top cap is formed in the second divot to provide a cap with a thickness of the gate cap and the top cap.