Self-Aligned Contact Structure for Gate Shoulder-Safe Etching
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Solution Overview
Problem
In semiconductor manufacturing, there is a trade-off between securing a bottom open margin of a contact plug and preventing the shoulder-loss of a gate structure during the etching process, which affects the integrity and performance of the semiconductor device.
Innovation Solution
A method involving a double sacrificial layer structure is employed to perform a high selectivity process, ensuring a bottom open margin of the contact plug and preventing the collapse of the gate structure's shoulder by forming a self-aligned contact with a concavely recessed top surface and inter-contact insulation patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a high selectivity etching process is used, then the bottom open margin of the contact plug is improved, but the shoulder of silicon nitride of the gate structure collapses
Solution Approach 1:
The patent introduces a double sacrificial layer structure (first sacrificial layer and second sacrificial layer) to segment the etching process into distinct stages. The first sacrificial layer protects the gate structure shoulder during initial etching, while the second sacrificial layer enables subsequent contact hole etching with high selectivity. This segmentation allows independent optimization of each etching stage without compromising the other.
Solution Approach 2:
The first sacrificial layer is formed and patterned before the contact hole etching process begins. This preliminary structure provides pre-protection to the gate structure shoulder, allowing the subsequent high selectivity etching to proceed without causing shoulder collapse. The preliminary action of forming the sacrificial layer enables the contact plug to achieve adequate bottom open margin while preserving gate structure integrity.
2Stability of the object's composition
If the selectivity of the etching process is lowered, then the shoulder of silicon nitride of the gate structure is prevented from collapsing, but the bottom open margin of the contact plug is compromised
Solution Approach 1:
The etching process is segmented into two distinct phases using the double sacrificial layer structure. The first phase uses the first sacrificial layer to protect the gate structure, allowing for controlled etching that preserves the shoulder. The second phase uses the second sacrificial layer to enable high selectivity etching for the contact hole, achieving adequate bottom open margin. This segmentation eliminates the need to compromise either parameter in a single etching step.
Solution Approach 2:
The double sacrificial layer structure acts as an intermediary between the gate structure and the contact hole etching process. The first sacrificial layer serves as a mediator that protects the gate structure shoulder during initial processing, while the second sacrificial layer mediates the subsequent contact hole formation. This intermediary structure enables the system to achieve both shoulder preservation and adequate bottom open margin that would be impossible in a direct single-step etching process.
Data Source
AI summary
A semiconductor device according to some embodiments of the disclosure may include a fin type active pattern extending in a first direction, a plurality of gate structures on the fin type active pattern and extending in a second direction different from the first direction, a plurality of inter-contact insulation patterns on respective ones of the plurality of gate structures, a plurality of interlayer insulation layers on side surfaces of the plurality of gate structures, and a plurality of contact plugs respectively between pairs of the plurality of gate structures. The fin type active pattern may include a plurality of source/drains. Lower ends of the plurality of contact plugs may contact the plurality of source/drains. The plurality of gate structures may each include a first gate metal, a second gate metal, a gate capping layer, a gate insulation layer, a first spacer, and a second spacer.


