Self-Aligned Contact Formation for Integrated Circuit Devices
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Solution Overview
Problem
Current methods for forming integrated circuit devices using photolithographically-defined patterning steps result in high failure rates and low yields due to unacceptably high rates of electrical shorts in high aspect ratio contact holes, as slight deviations in alignment can cause shorts between electrical interconnects and surrounding structures.
Innovation Solution
The method involves forming gate electrodes with sidewall spacers, covering them with insulating layers, and using these layers as masks to create self-aligned openings that are filled with conductive material, thereby compensating for alignment deviations and enhancing electrical isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If photolithographically-defined patterning steps are used to define circuit features, then lateral dimensions can be reduced, but alignment deviations cause electrical shorts in high aspect ratio contact holes
Solution Approach 1:
The method performs preliminary actions by forming sidewall spacers on gate electrodes before defining contact hole positions. These spacers serve as self-aligned masks that automatically compensate for alignment deviations during subsequent photolithography steps, ensuring precise contact hole placement even when alignment tolerances are exceeded
Solution Approach 2:
The sidewall spacers serve themselves as alignment references and masks for contact hole formation. The spacers automatically position the contact holes relative to the gate electrodes without requiring external alignment markers, making the system self-correcting for alignment errors
2Length of stationary object
If high aspect ratio contact holes are formed, then electrical interconnects can be created in deep structures, but slight alignment deviations cause electrical shorts between interconnects and surrounding structures
Solution Approach 1:
The method performs preliminary actions by forming protective insulating layers and sidewall spacers before contact hole etching. These structures are prepared in advance to ensure proper electrical isolation is maintained throughout the deep contact hole formation process, preventing shorts before they can occur
Solution Approach 2:
The method provides beforehand cushioning by depositing protective insulating layers on the sidewalls of contact holes before filling them with conductive material. These protective layers act as a cushion against misalignment, preventing electrical shorts even when alignment deviations occur during the high aspect ratio contact hole formation
3Length of moving object
If photolithographic alignment tolerances do not scale downward with reduced lateral dimensions, then manufacturing complexity increases, but yield and reliability deteriorate
Solution Approach 1:
The sidewall spacers serve themselves as alignment references that automatically adapt to the reduced lateral dimensions. The spacers maintain proportional dimensions relative to the gate electrodes, providing self-scaling alignment references that work across different device sizes without requiring adjusted alignment tolerances
Solution Approach 2:
The method changes parameters by using the sidewall spacer height and position as the controlling dimension for contact hole placement rather than relying on photolithographic alignment parameters. This parameter transformation decouples the contact hole positioning accuracy from the photolithographic alignment tolerances, allowing yield to be maintained even as lateral dimensions scale down
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces electrical shorts and improves yield by providing additional isolation between structures, even with slight deviations in photolithographic alignment, leading to more reliable integrated circuit device fabrication.
Implementation Method 1
The gate electrodes are covered with a first electrically insulating layer of a first material (e.g., silicon dioxide). A second electrically insulating layer of a second material (e.g., silicon nitride) is deposited on the first electrically insulating layer.
Implementation Method 2
The second electrically insulating layer is patterned to define a first opening therein that exposes an underlying first portion of the first electrically insulating layer. The first portion of the first electrically insulating layer is selectively etched to define a second opening therein
Implementation Method 3
sidewalls of the first and second openings, the first and second sidewall spacers and the exposed first portion of the substrate are conformally lined with an electrically insulating protective layer of the second material
Data Source
AI summary
Methods of forming integrated circuit devices include forming first and second gate electrodes at side-by-side locations on a substrate and forming first and second sidewall spacers on sidewalls of the first gate electrode and the second gate electrode, respectively. The first and second gate electrodes are covered with a first electrically insulating layer of a first material. A second electrically insulating layer of a second material is deposited on the first electrically insulating layer. The second electrically insulating layer is patterned to define a first opening therein that exposes an underlying first portion of the first electrically insulating layer.