Self-Aligned Contact Structure for High Voltage Integrated Circuits

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Solution Overview

Problem

Conventional semiconductor fabrication processes face challenges in accurately aligning contact structures for high voltage semiconductor devices, leading to voltage breakdown and increased costs due to limitations in feature size and process complexity.

Innovation Solution

A method for forming a self-aligned contact in high voltage semiconductor integrated circuit devices involves creating a semiconductor substrate with a contact region, forming a plasma enhanced oxide and stop layer, and using a silicide layer to create a silicided contact region, followed by an interdielectric layer and a contact plug layer, allowing for precise alignment without damaging the source/drain region.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional alignment methods are used for contact structures, then manufacturing process is simpler, but alignment precision deteriorates leading to voltage breakdown

Engineering Contradiction:

Improvecontact structure alignment precisionVSAvoidprocess complexity

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The method performs preliminary actions by forming the plasma enhanced oxide layer and stop layer before contact opening etching. These layers are prepared in advance with specific thicknesses and positions that will later serve as alignment references, enabling precise contact structure placement without requiring complex real-time alignment procedures

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The plasma enhanced oxide layer and stop layer serve dual functions: they act as etch stop layers during contact opening formation and simultaneously serve as alignment reference markers. The process self-aligns the contact structures to the source/drain regions using these reference layers, eliminating the need for separate complex alignment procedures

Inventive Principle:

Principle #25Self-service

2Productivity

If feature size is reduced to increase circuit density, then productivity improves, but manufacturing precision deteriorates due to process limits

Engineering Contradiction:

Improvecircuit densityVSAvoidfeature size control

Core Design Contradiction:

ProductivityVSManufacturing precision

Solution Approach 1:

The invention changes the parameter of layer thickness ratios rather than absolute dimensions. By controlling the plasma enhanced oxide layer thickness (50-200 nm) and stop layer thickness (100-500 nm) as proportional relationships, the method maintains precise alignment across different feature size generations, allowing circuit density to increase while preserving manufacturing precision through scalable parameter relationships

Inventive Principle:

Principle #35Parameter changes

3Reliability

If conventional etching processes are used, then manufacturing cost is lower, but reliability deteriorates due to source/drain region damage

Engineering Contradiction:

Improvesource/drain region integrityVSAvoidmanufacturing cost

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The plasma enhanced oxide layer serves as a cushioning protective layer formed beforehand between the etch process and the source/drain region. During contact opening etching, this layer absorbs etch damage that would otherwise reach the source/drain region, protecting it from damage while allowing conventional etching processes to be used without requiring expensive alternative etching methods

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances device yields and maintains high breakdown voltage characteristics, reducing costs and improving process compatibility with conventional technology, while avoiding defects associated with mis-aligned mask etching.

Implementation Method 1

forming a plasma enhanced oxide overlying surface region

Methodology Applied

Scientific EffectPlasma enhanced chemical vapor deposition: Plasma Enhanced Chemical Vapour Deposition

Data Source

PatentUS8507378B2Method and structure for self aligned contact for integrated circuits

Publication Date: 2013.08.13 SEMICON MFG INT (SHANGHAI) CORP

AI summary

A high voltage integrated circuit device includes a semiconductor substrate having a surface region with a contact region, which is coupled to a source/drain region. The device has a plasma enhanced oxide overlying the surface region, a stop layer overlying the plasma enhanced oxide, and a contact opening through a portion of the stop layer and through a portion of the plasma enhanced oxide layer. The contact opening exposes a portion of the contact region without damaging it. The device has a silicide layer overlying the contact region to form a silicided contact region and an interlayer dielectric overlying the silicided contact region to fill the contact opening and provide a thickness of material overlying the stop layer. An opening in the interlayer dielectric layer is formed through a portion of the thickness to expose a portion of the silicided contact region and expose a portion of the stop layer.