Self-Aligned Contact Pads for Semiconductor Integrated Circuits
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Solution Overview
Problem
Current semiconductor integrated circuit devices face challenges in forming contacts in both cell array and peripheral circuit regions due to differences in size, shape, function, and conductive materials, leading to increased contact resistance and complex processing requirements, especially with the reduction in design rules.
Innovation Solution
A method is developed to form self-aligned contact pads in both regions using selective epitaxial films, impurity implantation, and metal films, simplifying the process by forming preliminary gate electrode structures, spacers, and interlayer insulating films, which reduces contact resistance and improves electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate processes are used for forming contacts in cell array region and peripheral circuit region, then contact formation can be optimized for each region, but process complexity increases
Solution Approach 1:
The patent merges the contact formation processes for cell array region and peripheral circuit region into a single unified process. By using a common conductive material (polysilicon) and identical processing steps for both regions, the patent eliminates the need for separate process sequences, thereby reducing overall process complexity while maintaining contact formation quality through the self-aligned mechanism that works effectively in both regions
2Productivity
If design rule is reduced to increase integration density, then device capacity increases, but contact resistance increases and open margins decrease
Solution Approach 1:
The patent transitions from planar contact formation to three-dimensional elevated contact formation. By growing selective epitaxial films that elevate the source/drain regions above the substrate surface, the patent creates vertical contact paths that bypass the limitations of reduced horizontal dimensions. This dimensional transition allows contacts to maintain adequate size and spacing even when design rules are reduced, thereby preserving low contact resistance while achieving high integration density
3Ease of operation
If polysilicon is used as conductive material for peripheral circuit contacts, then material consistency is achieved, but additional impurity implantation processes are required for transistors with different conductivities
Solution Approach 1:
The patent applies local quality by performing impurity implantation selectively in different regions after forming the unified polysilicon conductive structure. By using photolithographic patterning to define region-specific implantation areas, the patent achieves the required different conductivities in cell array and peripheral circuit regions while maintaining material consistency throughout. This localized differentiation eliminates the need for separate conductive materials while still accommodating diverse transistor requirements
4Manufacturing precision
If self-aligned contacts are formed in cell array region, then alignment precision is improved, but the same approach cannot be applied to peripheral circuit region with different contact requirements
Solution Approach 1:
The patent creates a universal contact formation methodology that functions effectively in both cell array region and peripheral circuit region. The self-aligned approach using selectively grown epitaxial films serves as a multi-functional process that accommodates different contact requirements in different regions. The unified polysilicon-based conductive structure with region-specific impurity implantation enables the same basic process to deliver tailored contact characteristics for both self-aligned contacts in cell arrays and metal wire connections in peripheral circuits
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the contact formation process, reduces contact resistance, and enhances electrical characteristics by allowing simultaneous contact formation in both regions, addressing issues of open margins and leakage current deterioration.
Implementation Method 1
forming selective epitaxial films on the semiconductor substrate in the cell array region and the peripheral region, wherein each selective epitaxial film is formed on a region of the semiconductor substrate exposed between gate electrodes
Implementation Method 2
implanting impurities into at least some of the selective epitaxial films to form elevated source/drain regions in the cell array region and the peripheral circuit region
Data Source
AI summary
Embodiments of the invention provide a semiconductor integrated circuit device and a method for fabricating the device. In one embodiment, the method comprises forming a plurality of preliminary gate electrode structures in a cell array region and a peripheral circuit region of a semiconductor substrate; forming selective epitaxial films on the semiconductor substrate in the cell array region and the peripheral region; implanting impurities into at least some of the selective epitaxial films to form elevated source/drain regions in the cell array region and the peripheral circuit region; forming a first interlayer insulating film; and patterning the first interlayer insulating film to form a plurality of first openings exposing the elevated source/drain regions. The method further comprises forming a first ohmic film, a first barrier film, and a metal film; and removing portions of each of the metal film, the first barrier film, and the first ohmic film.