Self-Aligned Contact Patterning for Spacer-Bounded Semiconductor Vias

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Solution Overview

Problem

The miniaturization of integrated circuits (ICs) poses challenges in forming contact areas over active regions, requiring precise patterning techniques to ensure proper alignment and filling of spaces between spacers, while maintaining manufacturing yield and performance.

Innovation Solution

A patterning technique using a combination of clear tone and dark tone masks to form self-aligned contact areas, where the boundaries are defined by the masks and spacers, allowing for the formation of contact areas that fill the spaces between adjacent spacers, thereby improving landing areas and reducing contact resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional photolithography techniques are used for miniaturized devices, then manufacturing process simplicity is maintained, but manufacturing precision deteriorates due to difficulty in forming properly aligned contact areas

Engineering Contradiction:
Improvecontact area alignment precisionVSAvoidpatterning process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patterning process is divided into two separate photolithography steps: first forming mandrels with initial photoresist, then forming contact areas with a second photoresist layer. This segmentation allows each step to be optimized independently, achieving precise contact area alignment while maintaining manageable process complexity through modular fabrication steps.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Mandrels are formed in advance before contact areas are created. The preliminary mandrel structures serve as alignment references and spacing definitions, enabling subsequent contact area formation to be precisely positioned without requiring complex real-time alignment procedures.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If contact areas are formed to fill spaces between spacers, then contact resistance is reduced, but manufacturing precision requirements increase for proper spacing and alignment

Engineering Contradiction:
Improvecontact resistanceVSAvoidspacing and alignment precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The mandrel structures automatically define the spacing and positioning of contact areas through their physical presence and dimensions. The contact areas self-align to the mandrel boundaries, eliminating the need for complex external alignment procedures and reducing manufacturing precision requirements while ensuring proper spacing for low contact resistance.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The mandrels are formed beforehand to establish the precise spacing pattern. This preliminary action creates a physical template that guides subsequent contact area formation, ensuring proper spacing is achieved without requiring high precision in the second patterning step.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If landing areas for vias are increased, then device performance is improved, but device area occupancy increases

Engineering Contradiction:
Improvedevice performanceVSAvoidlanding area occupancy
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The mandrel structures extend in the vertical dimension, providing three-sided boundaries that define contact area positions. This dimensional approach allows landing areas to be enlarged for improved performance while efficiently utilizing the available planar space, as the vertical mandrel structures provide comprehensive boundary definition without excessive horizontal footprint.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS11978732B2Methods of manufacturing semiconductor devices
Publication Date: 2024.05.07 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11978732B2 patent drawing
  • US11978732B2 patent drawing
  • US11978732B2 patent drawing

AI summary

A method of manufacturing a semiconductor device includes forming a first masking layer and second masking layer over a substrate. The first masking layer includes an opening over an active area and a spacer in the substrate, and the second masking layer having a block blocks a portion of the opening in the first masking layer. The block in the second masking layer has boundaries located completely within the boundary of the opening in the first masking layer. The method includes performing an etching process, using the first masking layer and the second masking layer as an etching mask, to form a contact opening which exposes a portion of the active area and a portion of the spacer, and forming a contact plug in the contact opening and over the exposed portion of the active area and the exposed portion of the spacer.