Self-Aligned Contact Formation via Three-Step Planarization
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Solution Overview
Problem
The challenge in semiconductor device manufacturing lies in achieving high integration, reliability, and multifunctionality while maintaining high speed, which is complicated by the need for precise control over gate electrode heights and planarization processes to form self-aligned contacts effectively.
Innovation Solution
A method involving the formation of gate electrodes, capping patterns, and interlayer dielectric layers, followed by a three-step planarization process using different slurry compositions to expose capping patterns and form self-aligned active contacts, ensuring precise control and non-uniform stepped profiles for enhanced electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a single planarization process is used, then the manufacturing process is simple, but the gate electrode heights cannot be precisely controlled and capping patterns cannot be selectively exposed
Solution Approach 1:
The planarization process is divided into three sequential steps with different slurry compositions: first planarization to expose the hardmask pattern, second planarization to expose the barrier layer, and third planarization to expose the capping patterns. This segmentation allows precise control of gate electrode heights at different stages while maintaining manageable process complexity through systematic breakdown.
Solution Approach 2:
Different slurry compositions are used for each planarization step to achieve selective removal rates. The first slurry is optimized for hardmask removal, the second for barrier layer exposure, and the third for capping pattern exposure. This local optimization of slurry properties at different process stages enables precise height control without requiring overly complex unified processes.
2Manufacturing precision
If multiple planarization processes with different slurry compositions are used, then capping patterns can be selectively exposed and electrical characteristics improved, but the manufacturing process becomes more complex
Solution Approach 1:
The slurry composition parameters are systematically changed across the three planarization steps. Each slurry has optimized chemical and mechanical properties tailored to the specific layer being removed at that stage. This parameter optimization achieves precise capping pattern exposure while keeping the process sequence straightforward and systematic, balancing precision with manufacturability.
3Reliability
If gate electrodes have non-uniform heights, then self-aligned contacts can be formed with improved electrical characteristics, but the planarization control becomes more difficult
Solution Approach 1:
The gate electrodes are prepared with non-uniform heights through preliminary planarization steps before contact formation. The first two planarization processes pre-shape the electrode surfaces to the required profiles, ensuring that subsequent contact formation achieves optimal electrical characteristics. This preliminary action simplifies the overall control by establishing the height profile early in the process sequence.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of self-aligned contacts with improved electrical characteristics, allowing for high integration and reliability in semiconductor devices by precisely controlling the planarization and exposure of capping patterns, thus addressing the complexity of high-speed and multifunctional requirements.
Implementation Method 1
performing a first planarization process until the hardmask pattern is exposed, performing a second planarization process until exposing a portion of the barrier layer, and performing a third planarization process until completely exposing the first to fourth capping patterns
Data Source
AI summary
A method of manufacturing a semiconductor device includes forming on a substrate gate electrodes extending in a first direction and spaced apart from each other in a second direction, forming capping patterns on the gate electrodes, forming interlayer dielectric layer filling spaces between adjacent gate electrodes, forming a hardmask on the interlayer dielectric layer with an opening selectively exposing second to fourth capping patterns, using the hardmask as an etch mask to form holes in the interlayer dielectric layer between the second and third gate electrodes and between the third and fourth gate electrodes, forming a barrier layer and a conductive layer in the holes, performing a first planarization to expose the hardmask, performing a second planarization to expose a portion of the barrier layer covering the second to fourth capping patterns, and performing a third planarization to completely expose the first to fourth capping patterns.