Self-Aligned Contact Formation Using Sacrificial Gate Electrodes
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Solution Overview
Problem
The challenge in semiconductor manufacturing lies in forming self-aligned contacts with precise alignment and planarity, especially as feature sizes shrink, leading to complex lithography and etch techniques required for densely packed device regions, where misalignment can degrade or destroy device performance.
Innovation Solution
The method involves forming sacrificial gate electrodes with a gate cap layer, performing etching to define self-aligned contact openings, depositing conductive material, and using a planarization process to expose the sacrificial material plugs, which are then removed to define self-aligned contacts, simplifying the process by using a sacrificial material layer with similar polishing characteristics to silicon dioxide, facilitating easier planarization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithography and etch techniques are used to form contact openings in densely packed device regions, then contact openings can be formed, but alignment accuracy deteriorates and device performance may be degraded or destroyed
Solution Approach 1:
The patent applies preliminary action by forming sacrificial gate electrodes and gate cap layers before defining the contact openings. The sacrificial structures are prepared in advance to serve as alignment references during subsequent etching processes, ensuring precise contact opening placement without requiring complex lithography techniques.
Solution Approach 2:
The patent uses sacrificial gate electrodes and gate cap layers as intermediary structures that facilitate the formation of self-aligned contacts. These intermediary structures serve as temporary references that guide the etching process, enabling accurate contact opening formation, and are removed after serving their alignment function.
2Manufacturing precision
If multiple material layers are planarized to achieve a uniform surface, then surface uniformity is improved, but the planarization process becomes more difficult and complex
Solution Approach 1:
The patent applies homogeneity by forming a gate cap layer with polishing characteristics similar to silicon dioxide. This allows the gate cap layer to be planarized together with the silicon dioxide interlayer dielectric material using a single CMP process, avoiding the complexity of planarizing multiple dissimilar material layers with different polishing characteristics.
Solution Approach 2:
The patent merges the planarization of the gate cap layer with the planarization of the silicon dioxide interlayer dielectric material into a single CMP process. By combining these two planarization steps, the patent eliminates the need for separate planarization processes and reduces the overall process complexity while achieving a uniform surface.
3Productivity
If feature sizes are reduced to increase packing density, then circuit element density is improved, but the complexity of forming contact openings increases significantly
Solution Approach 1:
The patent applies self-service by forming self-aligned contacts where the sacrificial gate electrodes and gate cap layers automatically serve as alignment references for the contact opening formation. The structures self-align during the etching process without requiring additional complex lithography steps, enabling contact formation in densely packed regions while simplifying the overall process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the complexity of planarization and improves alignment accuracy, enhancing the reliability and performance of self-aligned contacts in semiconductor devices by maintaining a uniform surface, even in densely packed regions.
Implementation Method 1
performing at least one etching process to define a self-aligned contact opening between the plurality of spaced-apart sacrificial gate electrodes
Implementation Method 2
performing at least one planarization process to remove the gate cap layers to thereby expose an upper surface of each of the sacrificial gate electrodes
Implementation Method 3
depositing at least one layer of conductive material in said self-aligned contact opening
Data Source
AI summary
Disclosed herein is a method of forming self-aligned contacts for a semiconductor device. In one example, the method includes forming a plurality of spaced-apart sacrificial gate electrodes above a semiconducting substrate, wherein each of the gate electrodes has a gate cap layer positioned on the gate electrode, and performing at least one etching process to define a self-aligned contact opening between the plurality of spaced-apart sacrificial gate electrodes. The method further includes removing the gate cap layers to thereby expose an upper surface of each of the sacrificial gate electrodes, depositing at least one layer of conductive material in said self-aligned contact opening and removing portions of the at least one layer of conductive material that are positioned outside of the self-aligned contact opening to thereby define at least a portion of a self-aligned contact positioned in the self-aligned contact opening.