Self-Aligned Contact Formation Using Segmented Protection Barriers
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Solution Overview
Problem
As semiconductor feature sizes decrease and device densities increase, forming reliable self-aligned contacts becomes challenging due to increased aspect ratios, leading to over-etching issues and exposure of conductive gates, which results in shorts between the gate and the self-aligned contact.
Innovation Solution
A method involving a substrate with transistors, a mask layer, insulating spacers, a dielectric layer, a barrier layer, and a protection barrier is used to form a self-aligned contact opening, where the dielectric layer is partially removed using the protection barrier and mask layer as an etching mask, preventing exposure of the conductive gates and ensuring accurate contact formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the dielectric layer is removed to form a self-aligned contact opening, then the source/drain region is exposed for contact formation, but the conductive gate becomes exposed and shorts occur between the gate and the self-aligned contact
Solution Approach 1:
The patent segments the protective structure into multiple layers: a first protective layer covering the gate and a second protective layer covering the insulating spacer. This segmentation allows each layer to protect specific critical regions during the contact opening formation process, preventing shorts while enabling precise contact alignment.
Solution Approach 2:
The protective layers are formed preliminarily before the contact opening etch process. The first protective layer is deposited and patterned to cover the gate, and the second protective layer is deposited to cover the insulating spacer. These preliminary protective structures prevent gate exposure and shorts during subsequent etching operations.
2Productivity
If device density is increased by decreasing pitch between adjacent MOS devices, then more devices fit on a chip, but spacers are partially removed during self-aligned contact opening formation
Solution Approach 1:
The second protective layer is deposited preliminarily over the insulating spacer before the contact opening formation process. This preliminary protection prevents the spacer from being partially removed during etching, maintaining spacer integrity even when pitch between devices is reduced to increase density.
Solution Approach 2:
The second protective layer acts as an intermediary protective structure between the insulating spacer and the etching process. It mediates the interaction by absorbing the etching damage that would otherwise remove the spacer, allowing high-density device placement without compromising spacer integrity.
3Productivity
If aspect ratio of contact structures is increased to accommodate higher device density, then more devices fit on a chip, but over-etching occurs in the lateral direction
Solution Approach 1:
The patent converts the potential harm of over-etching into a benefit by using the protective layers as sacrificial elements. The first and second protective layers are designed to be removed after serving their protective function, transforming the lateral etch that would normally cause damage into a controlled removal process that maintains precision while enabling higher device density.
Data Source
AI summary
An integrated circuit with a self-aligned contact includes a substrate with a transistor formed thereover, a dielectric spacer, a protection barrier, and a conductive layer. The transistor includes a mask layer and a pair of insulating spacers formed on opposite sides of the mask layer. The dielectric spacer partially covers at least one of the insulating spacers of the transistor. The protection barrier is formed over the dielectric spacer. The conductive layer is formed over the mask layer, the protection barrier, the dielectric spacer, the insulating spacer and the dielectric spacer as a self-aligned contact for contacting a source/drain region of the transistor.