Self-Aligned Contact Formation for Semiconductor Scaling
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Solution Overview
Problem
As semiconductor processes scale down, fabricating back end of line (BEOL) and middle of line (MOL) metallization features becomes challenging due to critical dimension scaling and material limitations, leading to issues like contact shorts and size penalties in source and drain silicide contacts.
Innovation Solution
The development of self-aligned silicide contacts that extend between adjacent diffusion regions in a substrate, using a combination of deposition, patterning, and etching techniques to form structures that maintain electrical contact without shorting to adjacent gate structures, even at smaller technology nodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching processes are used to remove dielectric material adjacent to gate structures, then contact openings can be formed, but the low-k dielectric spacer material is eroded away exposing the gate metal structure resulting in shorts
Solution Approach 1:
A sacrificial oxide layer is introduced as an intermediary protective barrier between the etching process and the low-k dielectric spacer material. The oxide layer is selectively removed after serving its protective function, allowing the etching to proceed without damaging the gate structure during the process
Solution Approach 2:
The gate structure is pre-coated with a protective oxide layer before the etching process begins. This preliminary protective action ensures that the underlying low-k dielectric material is not eroded during subsequent etching operations that form contact openings
2Length of moving object
If lithographic limits are applied to shrinking device dimensions, then smaller features can be fabricated, but contact open issues result in narrow source and drain silicide contacts
Solution Approach 1:
The self-aligned contact structure utilizes the existing gate structure and spacer materials to automatically define the contact position and dimensions. The contact opens naturally between the spacers without requiring additional lithographic patterning steps, allowing the contact size to self-adjust according to the gate pitch
Solution Approach 2:
The contact formation process transitions from relying solely on planar lithographic patterning to utilizing the vertical dimension of the spacer structures. The contact openings are defined by the spacer height and alignment rather than by top-down lithographic patterns, enabling reliable contact formation at smaller dimensions
3Reliability
If larger sized silicide contacts are fabricated to solve contact open issues, then contact reliability improves, but a size penalty is incurred
Solution Approach 1:
The contact dimensions are determined by the self-aligned spacer structures rather than by deliberate oversizing. The contact area naturally adapts to the required size based on the gate pitch and spacer dimensions, eliminating the need for larger than necessary contact areas
Data Source
AI summary
The present disclosure relates to semiconductor structures and, more particularly, to self-aligned contacts and methods of manufacture. The structure includes: adjacent diffusion regions located within a substrate material; sidewall structures above an upper surface of the substrate material, aligned on sides of the adjacent diffusion regions; and a contact between the sidewall structures and extending to within the substrate material between and in electrical contact with the adjacent diffusion regions.