Self-Aligned Contact Spacer Alignment for Semiconductor Integration

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Solution Overview

Problem

Conventional semiconductor manufacturing processes with self-aligned contacts face misalignment issues and damage to shallow trench isolation structures, limiting device integration as the distance between isolation structures decreases, requiring larger preserved spaces to prevent holes.

Innovation Solution

The formation of spacers on the sidewalls of isolation and gate structures during the manufacturing process allows for self-aligned contact openings without using silicon nitride as an etching mask, simplifying the process and improving integration by avoiding misalignment and damage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If silicon nitride is used as an etching mask layer in the self-aligned contact process, then contact alignment can be achieved, but the shallow trench isolation structures are damaged and device integration is limited

Engineering Contradiction:
Improvecontact alignment precisionVSAvoiddamage to isolation structures
Core Design Contradiction:
Manufacturing precisionVSObject-affected harmful factors

Solution Approach 1:

The patent removes the silicon nitride etching mask layer from the conventional self-aligned contact process. Instead, it uses the spacer structure itself as the alignment reference, extracting the harmful mask layer that causes damage to isolation structures while maintaining contact alignment precision through the spacer-based self-alignment mechanism

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent employs a temporary spacer structure that serves as the alignment reference during the etching process, then is removed afterward. This disposable spacer structure replaces the damaging silicon nitride mask, providing the necessary alignment function without the harmful side effects

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

2Object-affected harmful factors

If larger preserved spaces are maintained between isolation structures, then damage prevention is achieved, but device integration density decreases

Engineering Contradiction:
Improvedamage prevention to isolation structuresVSAvoiddevice integration density
Core Design Contradiction:
Object-affected harmful factorsVSArea of stationary object

Solution Approach 1:

The spacer structure serves itself as the alignment reference for contact hole formation, eliminating the need for external etching mask layers. This self-aligned mechanism allows contact holes to be precisely positioned relative to the spacer, enabling tighter spacing between isolation structures without risking damage, thus improving device integration density

Inventive Principle:
Principle #25Self-service

3Area of stationary object

If the distance between isolation structures is decreased, then device integration is improved, but misalignment and damage risks increase

Engineering Contradiction:
Improvedevice integration densityVSAvoidcontact alignment precision
Core Design Contradiction:
Area of stationary objectVSManufacturing precision

Solution Approach 1:

The spacer structure is formed in advance on the isolation structures before the contact hole etching process. This preliminary spacer formation establishes precise alignment references that guide the subsequent contact hole positioning, ensuring accurate alignment even when isolation structures are closely spaced, thus enabling improved device integration without sacrificing precision

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS7612433B2Semiconductor device having self-aligned contact
Publication Date: 2009.11.03 NEXCHIP SEMICON CO LTD
  • US7612433B2 patent drawing
  • US7612433B2 patent drawing
  • US7612433B2 patent drawing

AI summary

A method of manufacturing semiconductor devices having self-aligned contacts is provided. Multiple isolation structures are formed on the substrate to define an active area. Multiple gate structures are formed on the substrate. Multiple doped areas are formed in the substrate beside each gate structure. Multiple first spacers are formed on the sidewalls of each of the gate structure. Multiple second spacers are formed on the sidewalls of each of the isolation structure. A dielectric layer is formed on the substrate. Then, a self-aligned process is performed to form multiple contact openings in the dielectric layer between the gate structures. The conductive material is filled in the contact openings.