Self-Aligned Source/Drain Contact Structure for Scaled Semiconductor Nodes
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Solution Overview
Problem
The semiconductor industry faces challenges in forming reliable semiconductor devices with increasingly smaller feature sizes due to the complexity and difficulty of fabrication processes as feature sizes continue to decrease, affecting production efficiency and costs.
Innovation Solution
The method involves forming gate structures and source/drain regions using a combination of photolithography, self-aligned processes, and epitaxial processes, along with the use of gate replacement and interlayer dielectric layers to create a semiconductor device with improved carrier mobility and reduced contact resistance, including the formation of gate spacers, epitaxy features, and dielectric liners to enhance device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes continue to decrease to increase functional density, then production efficiency and cost are improved, but fabrication process complexity and difficulty increase
Solution Approach 1:
The fabrication process is divided into multiple self-aligned steps including forming mandrels, depositing first spacers, removing mandrels, depositing second spacers, and selective removal. This segmentation allows complex patterning to be achieved through simpler, more controllable individual steps that can be manufactured with existing equipment
Solution Approach 2:
Mandrels are formed in advance as sacrificial structures to define the positions of subsequent features. The first and second spacers are deposited preliminarily to establish precise geometric relationships before final device formation. These preliminary structures guide the self-aligned process to achieve small features without requiring direct patterning at that scale
2Area of stationary object
If feature sizes continue to decrease to increase functional density, then chip area is reduced, but manufacturing reliability deteriorates
Solution Approach 1:
The self-aligned process allows previously formed structures to automatically define the positions of subsequent features without requiring additional alignment steps. The spacers self-align to the mandrels and gate structures, eliminating alignment errors that would compromise reliability at small feature sizes
Solution Approach 2:
The process uses selective removal of materials based on their chemical composition rather than relying solely on dimensional control. Different spacer materials or mandrel materials are removed selectively, providing a robust mechanism for feature definition that maintains reliability even as feature dimensions shrink
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the manufacturing of reliable semiconductor devices with improved carrier mobility and reduced contact resistance, enhancing device performance and efficiency while maintaining production feasibility despite the scaling down of feature sizes.
Implementation Method 1
forming gate structures and source/drain regions using a combination of photolithography, self-aligned processes
Implementation Method 2
epitaxial processes, along with the use of gate replacement and interlayer dielectric layers to create a semiconductor device with improved carrier mobility
Data Source
AI summary
A semiconductor device includes a semiconductor substrate, a gate electrode, a source/drain contact, a conductive structure, an interlayer dielectric (ILD) layer, an etch stop layer, and a dielectric liner. The semiconductor substrate has a channel region and a source/drain region. The gate electrode is over the channel region. The source/drain contact is over the source/drain region. The conductive structure is over a top surface of the source/drain contact. The ILD layer surrounds the conductive structure and over the gate electrode. The etch stop layer is over the conductive structure and the ILD layer. The etch stop layer comprises a material different from that of the ILD layer. A dielectric liner at a sidewall the conductive structure. The dielectric liner extends from the top surface of the source/drain contact to a bottom surface of the etch stop layer.